Issued Patents All Time
Showing 1–25 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11468923 | Apparatuses and methods for controlling data timing in a multi-memory system | Zer Liang | 2022-10-11 |
| 10748584 | Apparatuses and methods for controlling data timing in a multi-memory system | Zer Liang | 2020-08-18 |
| 10573371 | Systems and methods for controlling data strobe signals during read operations | — | 2020-02-25 |
| 10431293 | Systems and methods for controlling data strobe signals during read operations | — | 2019-10-01 |
| 10109327 | Apparatuses and methods for controlling data timing in a multi-memory system | Zer Liang | 2018-10-23 |
| 9715909 | Apparatuses and methods for controlling data timing in a multi-memory system | Zer Liang | 2017-07-25 |
| 9621167 | Logic circuit and method for controlling a setting circuit | — | 2017-04-11 |
| 9214926 | Three dimensional integrated circuit and method for controlling the same | — | 2015-12-15 |
| 9054675 | Apparatuses and methods for adjusting a minimum forward path delay of a signal path | Kallol Mazumder, Jongtae Kwak, Yasuo Satoh | 2015-06-09 |
| 8943389 | Signal transmission/reception circuit | — | 2015-01-27 |
| 8666256 | Optical transceiving system with frame synchronization and optical receiving apparatus | — | 2014-03-04 |
| 8656259 | Data transmission | — | 2014-02-18 |
| 8311173 | Frame pulse signal latch circuit and phase adjustment method | — | 2012-11-13 |
| RE43539 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit | — | 2012-07-24 |
| 8218701 | Communication system | — | 2012-07-10 |
| RE42659 | Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed | Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura | 2011-08-30 |
| 7821804 | Semiconductor integrated circuit | Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura | 2010-10-26 |
| 7795941 | Frame pulse signal latch circuit and phase adjustment method | — | 2010-09-14 |
| RE41379 | Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed | Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura | 2010-06-15 |
| RE40356 | Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed | Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura | 2008-06-03 |
| 7289346 | Semiconductor integrated circuit | Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura | 2007-10-30 |
| 7274613 | Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors | Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Yoshitaka Nakamura | 2007-09-25 |
| 7030438 | Semiconductor integrated circuit | Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura | 2006-04-18 |
| RE38944 | Semiconductor memory | Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura | 2006-01-24 |
| 6944080 | Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors | Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Yoshitaka Nakamura | 2005-09-13 |