Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11468923 | Apparatuses and methods for controlling data timing in a multi-memory system | Tsugio Takahashi | 2022-10-11 |
| 11373725 | Error correction code circuits having one-to-one relationships with input/output pads and related apparatuses and methods | Minari Arai, Takuya Nakanishi | 2022-06-28 |
| 10748584 | Apparatuses and methods for controlling data timing in a multi-memory system | Tsugio Takahashi | 2020-08-18 |
| 10109327 | Apparatuses and methods for controlling data timing in a multi-memory system | Tsugio Takahashi | 2018-10-23 |
| 9715909 | Apparatuses and methods for controlling data timing in a multi-memory system | Tsugio Takahashi | 2017-07-25 |
| 9466348 | Method and apparatus for memory command input and control | Jacob Anderson, Kang-Yong Kim, Tadashi Yamamoto, Huy T. Vo | 2016-10-11 |
| 9059053 | Multi-die stack structure | Kotaro Suzuki | 2015-06-16 |
| 8913447 | Method and apparatus for memory command input and control | Jacob Anderson, Kang-Yong Kim, Tadashi Yamamoto, Huy T. Vo | 2014-12-16 |
| 8520452 | Data bus power-reduced semiconductor storage apparatus | Takuya Nakanishi | 2013-08-27 |
| 8194474 | Data bus power-reduced semiconductor storage apparatus | Takuya Nakanishi | 2012-06-05 |
| 8004909 | Data bus power-reduced semiconductor storage apparatus | Takuya Nakanishi | 2011-08-23 |
| 7746710 | Data bus power-reduced semiconductor storage apparatus | Takuya Nakanishi | 2010-06-29 |