Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11472915 | Porous compositions and related methods | Timothy M. Swager, Zachary Smith, Sharon Sheau-Pyng Lin, Francesco Maria Benedetti | 2022-10-18 |
| 11443788 | Reference-voltage-generators within integrated assemblies | Takamasa Suzuki, Yasuo Satoh, Hyunui Lee | 2022-09-13 |
| 11443780 | Vertical access line multiplexor | Beau D. Barry, Tae H. Kim, Christopher John Kawamura | 2022-09-13 |
| 11423972 | Integrated assemblies | Jiyun Li | 2022-08-23 |
| 11423973 | Contemporaneous sense amplifier timings for operations at internal and edge memory array mats | — | 2022-08-23 |
| 11398266 | Integrated assemblies having memory cells with capacitive units and reference-voltage-generators with resistive units | Hyunui Lee, Takamasa Suzuki, Yasuo Satoh | 2022-07-26 |
| 11386948 | Multiplexors under an array of memory cells | Tae H. Kim | 2022-07-12 |
| 11380387 | Multiplexor for a semiconductor device | Tae H. Kim | 2022-07-05 |
| 11380376 | Apparatuses and methods to perform low latency access of a memory | Daigo Toyama | 2022-07-05 |
| 11367476 | Bit line equalization driver circuits and related apparatuses, methods, and computing systems to avoid degradation of pull-down transistors | Sang-Kyun Park | 2022-06-21 |
| 11361814 | Column selector architecture with edge mat optimization | Hiroshi Akamatsu | 2022-06-14 |
| 11302377 | Apparatuses and methods for dynamic targeted refresh steals | Liang Li, Yu Zhang | 2022-04-12 |
| 11290103 | Charge transfer between gate terminals of subthreshold current reduction circuit transistors and related apparatuses and methods | Hiroshi Akamatsu, Toru Ishikawa | 2022-03-29 |
| 11282569 | Apparatus with latch balancing mechanism and methods for operating the same | Hiroshi Akamatsu | 2022-03-22 |
| 11250903 | Apparatus for supplying power supply voltage to semiconductor chip including volatile memory cell | Chikara Kondo, Daigo Toyama | 2022-02-15 |
| 11237734 | High throughput DRAM with distributed column access | — | 2022-02-01 |
| 11237579 | Apparatuses and methods for ZQ calibration | Yasuo Satoh | 2022-02-01 |
| 11217297 | Techniques for reducing row hammer refresh | Yutaka Ito | 2022-01-04 |
| 11170841 | Apparatus with extended digit lines and methods for operating the same | Sang-Kyun Park | 2021-11-09 |
| 11152050 | Apparatuses and methods for multiple row hammer refresh address sequences | Masaru Morohashi, Ryo Nagoshi, Yutaka Ito | 2021-10-19 |
| 11150686 | Apparatuses for reducing clock path power consumption in low power dynamic random access memory | — | 2021-10-19 |
| 11144778 | Descriptor guided fast marching method for analyzing images and systems using the same | Hong Chen | 2021-10-12 |
| 11087827 | Edge memory array mats with sense amplifiers | — | 2021-08-10 |
| 11081160 | Apparatus and methods for triggering row hammer address sampling | Yutaka Ito | 2021-08-03 |
| 11070232 | Multi channel memory with flexible code-length ECC | Yutaka Ito | 2021-07-20 |