Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7102937 | Solution to DQS postamble ringing problem in memory chips | Sugato Mukherjee, Christopher K. Morzano | 2006-09-05 |
| 7093095 | Double data rate scheme for data output | Mark R. Thomann | 2006-08-15 |
| 7054222 | Write address synchronization useful for a DDR prefetch SDRAM | Christopher K. Morzano | 2006-05-30 |
| 6968026 | Method and apparatus for output data synchronization with system clock in DDR | Aaron Schoenfeld | 2005-11-22 |
| 6954388 | Delay locked loop control circuit | Mark R. Thomann | 2005-10-11 |
| 6922367 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Christopher K. Morzano | 2005-07-26 |
| 6901013 | Controller for delay locked loop circuits | William F. Jones, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller | 2005-05-31 |
| 6836437 | Method of reducing standby current during power down mode | Mark R. Thomann, Daniel R. Loughmiller, Scott E. Schaefer | 2004-12-28 |
| 6819603 | Method of controlling a delay locked loop | William F. Jones | 2004-11-16 |
| 6809974 | Controller for delay locked loop circuits | William F. Jones, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller | 2004-10-26 |
| 6809990 | Delay locked loop control circuit | Mark R. Thomann | 2004-10-26 |
| 6763444 | Read/write timing calibration of a memory array using a row or a redundant row | Mark R. Thomann, Christopher K. Morzano | 2004-07-13 |
| 6724670 | Shared redundancy for memory having column addressing | William F. Jones | 2004-04-20 |
| 6704881 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Aaron Schoenfeld, R. Jacob Baker | 2004-03-09 |
| 6694416 | Double data rate scheme for data output | Mark R. Thomann | 2004-02-17 |
| 6691214 | DDR II write data capture calibration | Christopher K. Morzano | 2004-02-10 |
| 6665219 | Method of reducing standby current during power down mode | Mark R. Thomann, Daniel R. Loughmiller, Scott E. Schaefer | 2003-12-16 |
| 6643194 | Write data masking for higher speed drams | Kevin J. Ryan, Christopher K. Morzano | 2003-11-04 |
| 6624660 | CMOS output driver for semiconductor device and related method for improving latch-up immunity in a CMOS output driver | Michael Chaine, Manny K. F. Ma | 2003-09-23 |
| 6600691 | High frequency range four bit prefetch output data path | Christopher K. Morzano | 2003-07-29 |
| 6556494 | High frequency range four bit prefetch output data path | Christopher K. Morzano | 2003-04-29 |
| 6532180 | Write data masking for higher speed DRAMs | Kevin J. Ryan, Christopher K. Morzano | 2003-03-11 |
| 6480429 | Shared redundancy for memory having column addressing | William F. Jones | 2002-11-12 |
| 6446180 | Memory device with synchronized output path | Christopher K. Morzano | 2002-09-03 |
| 6438060 | Method of reducing standby current during power down mode | Mark R. Thomann, Daniel R. Loughmiller, Scott E. Schaefer | 2002-08-20 |