Issued Patents All Time
Showing 101–125 of 301 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9721960 | Data line arrangement and pillar arrangement in apparatuses | — | 2017-08-01 |
| 9711514 | Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate | — | 2017-07-18 |
| 9711228 | Apparatus and methods of operating memory with erase de-bias | — | 2017-07-18 |
| 9711224 | Devices including memory arrays, row decoder circuitries and column decoder circuitries | — | 2017-07-18 |
| 9704876 | Semiconductor apparatus with multiple tiers, and methods | — | 2017-07-11 |
| 9697907 | Apparatuses and methods using dummy cells programmed to different states | Aaron Yip | 2017-07-04 |
| 9646660 | Selectable memory access time | — | 2017-05-09 |
| 9641068 | Voltage generator circuit | — | 2017-05-02 |
| 9614516 | Devices for shielding a signal line over an active region | — | 2017-04-04 |
| 9607705 | Apparatuses and methods for charging a global access line prior to accessing a memory | — | 2017-03-28 |
| 9595533 | Memory array having connections going through control gates | Tamotsu Murakoshi, Deepak Thimmegowda | 2017-03-14 |
| 9536582 | Enable/disable of memory chunks during memory access | Satoru Tamada, Koichi Kawai, Tetsuji Manabe | 2017-01-03 |
| 9536618 | Apparatuses and methods to control body potential in memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu +2 more | 2017-01-03 |
| 9437253 | Memory devices having data lines included in top and bottom conductive lines | — | 2016-09-06 |
| 9430417 | Sequential memory access operations | — | 2016-08-30 |
| 9424936 | Current leakage reduction in 3D NAND memory | Akira Goda, Shigekazu Yamada, Hiroyuki Sanda | 2016-08-23 |
| 9412451 | Apparatuses and methods using dummy cells programmed to different states | Aaron Yip | 2016-08-09 |
| 9401188 | Devices and systems including enabling circuits | Ali Feiz Zarrin Ghalam | 2016-07-26 |
| 9378823 | Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the memory cell to a second voltage to indicate the data value | — | 2016-06-28 |
| 9368216 | Interconnections for 3D memory | — | 2016-06-14 |
| 9349470 | Memory read apparatus and methods | — | 2016-05-24 |
| 9343479 | Three-dimensional devices having reduced contact length | — | 2016-05-17 |
| 9330789 | Short-checking methods | — | 2016-05-03 |
| 9324443 | Compensating for off-current in a memory | — | 2016-04-26 |
| 9318173 | Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information | — | 2016-04-19 |