Issued Patents All Time
Showing 76–100 of 301 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10090051 | Memory array with power-efficient read architecture | — | 2018-10-02 |
| 10083265 | Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information | — | 2018-09-25 |
| 10079064 | Apparatuses and methods using dummy cells programmed to different states | Aaron Yip | 2018-09-18 |
| 10079063 | Apparatuses and methods for charging a global access line prior to accessing a memory | — | 2018-09-18 |
| 10050049 | Apparatuses including memory arrays with source contacts adjacent edges of sources | — | 2018-08-14 |
| 10049750 | Methods including establishing a negative body potential in a memory cell | Koji Sakui, Mark Hawes, Jeremy Binfet | 2018-08-14 |
| 10014057 | Devices including memory arrays, row decoder circuitries and column decoder circuitries | — | 2018-07-03 |
| 9996438 | Chunk redundancy architecture for memory | — | 2018-06-12 |
| 9953711 | Methods of operating memory under erase conditions | — | 2018-04-24 |
| 9910594 | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation | Shantanu R. Rajwade, Pranav Kalavade | 2018-03-06 |
| 9905514 | Semiconductor device structures including staircase structures, and related methods and electronic systems | — | 2018-02-27 |
| 9892797 | Apparatuses and methods for charging a global access line prior to accessing a memory | — | 2018-02-13 |
| 9881686 | Apparatuses and methods to control body potential in 3D non-volatile memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu +2 more | 2018-01-30 |
| 9881651 | Interconnections for 3D memory | — | 2018-01-30 |
| 9842652 | Memory array with power-efficient read architecture | — | 2017-12-12 |
| 9786334 | Interconnections for 3D memory | — | 2017-10-10 |
| 9778846 | Sequential memory access operations | — | 2017-10-03 |
| 9779791 | Apparatuses and methods involving accessing distributed sub-blocks of memory cells | — | 2017-10-03 |
| 9779819 | Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells | Qiang Tang, Ramin Ghodsi | 2017-10-03 |
| 9780110 | Memory having memory cell string and coupling components | — | 2017-10-03 |
| 9773564 | Memory read apparatus and methods | — | 2017-09-26 |
| 9773553 | Segmented memory and operation | Han Zhao | 2017-09-26 |
| 9747991 | Random telegraph signal noise reduction scheme for semiconductor memories | — | 2017-08-29 |
| 9728538 | Three-dimensional devices having reduced contact length | — | 2017-08-08 |
| 9727417 | Chunk redundancy architecture for memory | — | 2017-08-08 |