Issued Patents All Time
Showing 26–50 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11081497 | Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies | Richard J. Hill, Byeung Chul Kim, Akira Goda | 2021-08-03 |
| 11081498 | Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies | Richard J. Hill | 2021-08-03 |
| 11037956 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan | 2021-06-15 |
| 11031414 | Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies | John D. Hopkins | 2021-06-08 |
| 11024644 | Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies | John D. Hopkins, Jordan D. Greenlee | 2021-06-01 |
| 10930652 | Apparatuses including buried digit lines | Suraj Mathew | 2021-02-23 |
| 10923480 | Capacitance reduction in a semiconductor device | Litao Yang, Gurtej S. Sandhu, Richard J. Hill | 2021-02-16 |
| 10777576 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan | 2020-09-15 |
| 10347634 | Apparatuses including buried digit lines | Suraj Mathew | 2019-07-09 |
| 9947666 | Semiconductor device structures including buried digit lines and related methods | Suraj Mathew | 2018-04-17 |
| 9847340 | Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices | Darwin Franseda Fan, Sateesh Koka, Gordon A. Haller, John D. Hopkins, Anish A. Khandekar | 2017-12-19 |
| 9773677 | Semiconductor device structures with doped elements and methods of formation | — | 2017-09-26 |
| 9691773 | Silicon buried digit line access device and method of forming the same | Lars Heineck | 2017-06-27 |
| 9559201 | Vertical memory devices, memory arrays, and memory devices | — | 2017-01-31 |
| 9478550 | Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors | Kamal M. Karda, Wolfgang Mueller, Sanh D. Tang | 2016-10-25 |
| 9318493 | Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions | Lars Heineck, Jaydip Guha | 2016-04-19 |
| 9230968 | Methods of forming memory arrays and semiconductor constructions | Jaydip Guha | 2016-01-05 |
| 9111853 | Methods of forming doped elements of semiconductor device structures | — | 2015-08-18 |
| 9111879 | Semiconductor processing methods, and methods for forming silicon dioxide | — | 2015-08-18 |
| 9070584 | Buried digitline (BDL) access device and memory array | Lars Heineck | 2015-06-30 |
| 9070767 | Vertical memory devices and apparatuses | — | 2015-06-30 |
| 9054216 | Methods of forming a vertical transistor | Jaydip Guha, Suraj Mathew, Kamal M. Karda, Hung-Ming Tsai | 2015-06-09 |
| 9041099 | Single-sided access device and fabrication method thereof | Sheng-Wei Yang | 2015-05-26 |
| 9012303 | Method for fabricating semiconductor device with vertical transistor structure | Sheng-Wei Yang, Ying-Cheng Chuang | 2015-04-21 |
| 8946018 | Methods of forming memory arrays and semiconductor constructions | Jaydip Guha | 2015-02-03 |