Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5196364 | Method of making a stacked capacitor dram cell | Pierre C. Fazan, Charles H. Dennison, Yauh-Ching Liu | 1993-03-23 |
| 5192872 | Cell structure for erasable programmable read-only memories | — | 1993-03-09 |
| 5177030 | Method of making self-aligned vertical intrinsic resistance | Monte Manning | 1993-01-05 |
| 5155057 | Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line | Charles H. Dennison, Pierre C. Fazan, Yauh-Ching Liu | 1992-10-13 |
| 5149665 | Conductive source line for high density programmable read-only memory applications | — | 1992-09-22 |
| 5126290 | Method of making memory devices utilizing one-sided ozone teos spacers | Tyler Lowrey | 1992-06-30 |
| 5122848 | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance | Fernando Gonzalez | 1992-06-16 |
| 5089867 | High control gate/floating gate coupling for EPROMs, E.sup.2 PROMs, and Flash E.sup.2 PROMs | — | 1992-02-18 |
| 5077225 | Process for fabricating a stacked capacitor within a monolithic integrated circuit using oxygen implantation | — | 1991-12-31 |
| 5073509 | Blanket CMOS channel-stop implant | — | 1991-12-17 |
| 5069747 | Creation and removal of temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on exposed, permanent silicon dioxide structures | David A. Cathey, Mark E. Tuttle, Tyler Lowrey | 1991-12-03 |
| 5066606 | Implant method for advanced stacked capacitors | — | 1991-11-19 |
| 5043780 | DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance | Pierre C. Fazan | 1991-08-27 |
| 5037773 | Stacked capacitor doping technique making use of rugged polysilicon | Fernando Gonzalez | 1991-08-06 |
| 5026657 | Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions | Tyler Lowrey, Fernando Gonzalez, Joseph Karniewicz, Pierre C. Fazan | 1991-06-25 |
| 5024961 | Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices | Aftab Ahmad | 1991-06-18 |
| 5023190 | CMOS processes | Fernando Gonzalez | 1991-06-11 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Charles H. Dennison, Yauh-Ching Liu +3 more | 1991-05-07 |
| 4981810 | Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers | Pierre C. Fazan, Charles H. Dennison, Yauh-Ching Liu | 1991-01-01 |
| 4971655 | Protection of a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon dioxide and silicon nitride | James J. Stefano | 1990-11-20 |
| 4959325 | Reduction of electric field effect in the bird's beak region of a DRAM cell following expansion of active region through local encroachment reduction | D. Mark Durcan | 1990-09-25 |
| 4924119 | Electrically programmable erasable inverter device with deprogramming limitation | — | 1990-05-08 |
| 4839301 | Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants | — | 1989-06-13 |