Issued Patents All Time
Showing 176–200 of 225 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6066559 | Method for forming a semiconductor connection with a top surface having an enlarged recess | Fernando Gonzalez, Guy T. Blalock | 2000-05-23 |
| 6060783 | Self-aligned contact plugs | Werner Juengling, Gordon A. Haller, David J. Keller, Tyler Lowrey | 2000-05-09 |
| 6057200 | Method of making a field effect transistor having an elevated source and an elevated drain | Pai-Hung Pan, Sujit Sharan | 2000-05-02 |
| 6043151 | Method for forming a semiconductor connection with a top surface having an enlarged recess | Fernando Gonzalez, Guy T. Blalock | 2000-03-28 |
| 6010953 | Method for forming a semiconductor buried contact with a removable spacer | — | 2000-01-04 |
| 6005801 | Reduced leakage DRAM storage unit | Zhiqiang Wu, Randhir P. S. Thakur, Alan R. Reinberg | 1999-12-21 |
| 5998844 | Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon | Pai-Hung Pan, Sujit Sharan | 1999-12-07 |
| 5994220 | Method for forming a semiconductor connection with a top surface having an enlarged recess | Fernando Gonzalez, Guy T. Blalock | 1999-11-30 |
| 5990021 | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture | Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu, Philip J. Ireland | 1999-11-23 |
| 5986347 | Processing methods of forming contact openings and integrated circuitry | Kevin G. Donohoe | 1999-11-16 |
| 5976985 | Processing methods of forming contact openings and integrated circuitry | Kevin G. Donohoe | 1999-11-02 |
| 5976976 | Method of forming titanium silicide and titanium by chemical vapor deposition | Trung T. Doan, Gurtej S. Sandhu, Sujit Sharan | 1999-11-02 |
| 5965923 | Lateral bipolar transistor and apparatus using same | Mike Violette | 1999-10-12 |
| 5958796 | Method for cleaning waste matter from the backside of a semiconductor wafer substrate | Guy T. Blalock | 1999-09-28 |
| 5945726 | Lateral bipolar transistor | Mike Violette | 1999-08-31 |
| 5945348 | Method for reducing the heights of interconnects on a projecting region with a smaller reduction in the heights of other interconnects | Guy T. Blalock, Scott Meikle, Sung-Cheol Kim | 1999-08-31 |
| 5945698 | Field effect transistor assemblies and transistor gate block stacks | — | 1999-08-31 |
| 5940712 | Method of forming a resistor and integrated circuitry having a resistor construction | Pierre C. Fazan, Aftab Ahmad, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1999-08-17 |
| 5929476 | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors | — | 1999-07-27 |
| 5923078 | Method of forming a resistor and integrated circuitry having a resistor construction | Pierre C. Fazan, Aftab Ahmad, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1999-07-13 |
| 5905295 | Reduced pitch laser redundancy fuse bank structure | Tod S. Stone, Paul S. Zagar | 1999-05-18 |
| 5892285 | Semiconductor connection with a top surface having an enlarged recess | Fernando Gonzalez, Guy T. Blalock | 1999-04-06 |
| 5866453 | Etch process for aligning a capacitor structure and an adjacent contact corridor | Pierre C. Fazan, Trung T. Doan, Tyler Lowrey | 1999-02-02 |
| 5858865 | Method of forming contact plugs | Werner Juengling, Gordon A. Haller, David J. Keller, Tyler Lowrey | 1999-01-12 |
| 5849615 | Semiconductor processing method of fabricating field effect transistors | Aftab Ahmad | 1998-12-15 |