Issued Patents All Time
Showing 76–100 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6452867 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2002-09-17 |
| 6449679 | RAM controller interface device for RAM compatibility (memory translator hub) | — | 2002-09-10 |
| 6445636 | Method and system for hiding refreshes in a dynamic random access memory | Brent Keeth, Brian M. Shirley, Charles H. Dennison | 2002-09-03 |
| 6442644 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | David Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac Michael O'Connell +9 more | 2002-08-27 |
| 6418495 | Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus | — | 2002-07-09 |
| 6415340 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2002-07-02 |
| 6405280 | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence | — | 2002-06-11 |
| 6374360 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Brent Keeth, Terry R. Lee, Troy A. Manning | 2002-04-16 |
| 6356506 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2002-03-12 |
| 6330637 | Synchronous DRAM modules including multiple clock out signals for increasing processing speed | — | 2001-12-11 |
| 6327216 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2001-12-04 |
| 6292877 | Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus | — | 2001-09-18 |
| 6286062 | Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus | — | 2001-09-04 |
| 6272608 | Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals | Terry R. Lee | 2001-08-07 |
| 6253278 | Synchronous DRAM modules including multiple clock out signals for increasing processing speed | — | 2001-06-26 |
| 6247070 | Pipelined packet-oriented memory system having a undirectional command and address bus and a bidirectional data bus | — | 2001-06-12 |
| 6233199 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2001-05-15 |
| 6172893 | DRAM with intermediate storage cache and separate read and write I/O | — | 2001-01-09 |
| 6044429 | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2000-03-28 |
| 5991850 | Synchronous DRAM modules including multiple clock out signals for increasing processing speed | — | 1999-11-23 |
| 5966724 | Synchronous memory device with dual page and burst mode operations | — | 1999-10-12 |
| 5935263 | Method and apparatus for memory array compressed data testing | Brent Keeth, Troy A. Manning, Chris G. Martin, Kim Pierce, Wallace E. Fister +3 more | 1999-08-10 |
| 5930198 | Memory having a plurality of external clock signal inputs | — | 1999-07-27 |
| 5923611 | Memory having a plurality of external clock signal inputs | — | 1999-07-13 |
| 5903509 | Memory device with multiple internal banks and staggered command execution | Jeffrey P. Wright | 1999-05-11 |