Issued Patents All Time
Showing 51–75 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6941415 | DRAM with hidden refresh | — | 2005-09-06 |
| 6907493 | Memory device interface | — | 2005-06-14 |
| 6895474 | Synchronous DRAM with selectable internal prefetch size | Christopher Johnson | 2005-05-17 |
| 6862654 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Charles H. Dennison | 2005-03-01 |
| 6851016 | System latency levelization for read data | Jeffery W. Janzen, Brent Keeth, Troy A. Manning, Brian Johnson | 2005-02-01 |
| 6845460 | Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register | Terry R. Lee, Joseph M. Jeddeloh | 2005-01-18 |
| 6842393 | Method for selecting one or a bank of memory devices | Brent Keeth | 2005-01-11 |
| 6789175 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2004-09-07 |
| 6735709 | Method of timing calibration using slower data rate pattern | Terry R. Lee, Joseph M. Jeddeloh | 2004-05-11 |
| 6725319 | Memory device interface memory translator hub | — | 2004-04-20 |
| 6662304 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Brent Keeth, Terry R. Lee, Troy A. Manning | 2003-12-09 |
| 6662266 | Synchronous DRAM modules with multiple clock out signals | — | 2003-12-09 |
| 6658523 | System latency levelization for read data | Jeffery W. Janzen, Brent Keeth, Troy A. Manning, Brian Johnson | 2003-12-02 |
| 6643194 | Write data masking for higher speed drams | Christopher K. Morzano, Wen Li | 2003-11-04 |
| 6621496 | Dual mode DDR SDRAM/SGRAM | — | 2003-09-16 |
| 6614698 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2003-09-02 |
| 6615325 | Method for switching between modes of operation | Jeffrey S. Mailloux, Todd A. Merritt, Brett Williams | 2003-09-02 |
| 6611885 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2003-08-26 |
| 6560668 | Method and apparatus for reading write-modified read data in memory device providing synchronous data transfers | Terry R. Lee | 2003-05-06 |
| 6560669 | Double data rate synchronous memory with block-write | — | 2003-05-06 |
| 6556483 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2003-04-29 |
| 6535450 | Method for selecting one or a bank of memory devices | Brent Keeth | 2003-03-18 |
| 6532180 | Write data masking for higher speed DRAMs | Christopher K. Morzano, Wen Li | 2003-03-11 |
| 6525981 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2003-02-25 |
| 6466507 | DRAM with intermediate storage cache and separate read and write I/O | — | 2002-10-15 |