Issued Patents All Time
Showing 26–50 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12131788 | Read counter adjustment for delaying read disturb scans | Nicola Ciocchini, Animesh Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei +1 more | 2024-10-29 |
| 12131028 | Programming selective word lines during an erase operation in a memory device | Jeffrey S. McNeil, Ugo Russo, Akira Goda, Kishore Kumar Muchherla, Violante Moschiano +2 more | 2024-10-29 |
| 12124322 | Access operation status signaling for memory systems | Qing Liang, Giuseppe Cariello, Deping He | 2024-10-22 |
| 12111724 | Redundant array management techniques | Chun Sum Yeung, Deping He, Xiangang Luo, Reshmi Basu | 2024-10-08 |
| 12105967 | Two-tier defect scan management | Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Lakshmi Kalpana Vakati +1 more | 2024-10-01 |
| 12099725 | Code rate as function of logical saturation | Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Akira Goda | 2024-09-24 |
| 12099449 | Using a flag to indicate whether a mapping entry points to sequentially stored data | Giuseppe Cariello | 2024-09-24 |
| 12086077 | Increased efficiency obfuscated logical-to-physical map management | Nadav Grosz | 2024-09-10 |
| 12086027 | Methods and system with dynamic ECC voltage and frequency | Nadav Grosz, David Aaron Palmer, Christian M. Gyllenskog | 2024-09-10 |
| 12079481 | Memory block erase protocol | Chun Sum Yeung, Deping He, Ting Luo, Guang Hu | 2024-09-03 |
| 12079479 | Memory device with multiple input/output interfaces | Chang Hua Siau | 2024-09-03 |
| 12056518 | Notifying memory system of host events via modulated reset signals | Qing Liang, Kulachet Tanpairoj, Stephen Hanna | 2024-08-06 |
| 12050773 | Completion flag for memory operations | Giuseppe Cariello | 2024-07-30 |
| 12019884 | Identification and storage of boot information at a memory system | Luca Porzio, Roberto Izzi, Christian M. Gyllenskog, Giuseppe Cariello, Reshmi Basu | 2024-06-25 |
| 12019557 | Padding cached data with valid data for memory flush commands | Kishore Kumar Muchherla, Akira Goda | 2024-06-25 |
| 12007903 | Dual address encoding for logical-to-physical mapping | Giuseppe Cariello | 2024-06-11 |
| 12002531 | Techniques for retiring blocks of a memory system | Deping He, Chun Sum Yeung | 2024-06-04 |
| 12001358 | Status check using signaling from a memory device | Reshmi Basu | 2024-06-04 |
| 11995353 | Storing parity during refresh operations | Reshmi Basu | 2024-05-28 |
| 11994947 | Multi-layer code rate architecture for special event protection with reduced performance penalty | Kishore Kumar Muchherla, Huai-Yuan Tseng, Mustafa N. Kaynak, Akira Goda, Sivagnanam Parthasarathy | 2024-05-28 |
| 11989138 | Host assisted operations in managed memory devices | Nadav Grosz | 2024-05-21 |
| 11983423 | Host recovery for a stuck condition | Deping He | 2024-05-14 |
| 11977778 | Workload-based scan optimization | Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Lakshmi Kalpana Vakati | 2024-05-07 |
| 11977667 | Purging data at a memory device | Christian M. Gyllenskog | 2024-05-07 |
| 11966272 | Storage device deep idle power mode | Qing Liang | 2024-04-23 |