Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10825446 | Training artificial intelligence to respond to user utterances | Aaron T. Smith, Andrew R. Freed, Joshua Allen, Ryan Brink, Sorabh Murgai | 2020-11-03 |
| 10699768 | Apparatuses and methods for command signal delay | Vijayakrishna J. Vankayala | 2020-06-30 |
| 10685696 | Apparatuses and methods for access based refresh timing | Daniel B. Penney | 2020-06-16 |
| 10534686 | Apparatuses and methods for address detection | Kallol Mazumder, Derek R. May, Jeffrey E. Koelling, Roger D. Norwood | 2020-01-14 |
| 10438646 | Apparatuses and methods for providing power for memory refresh operations | Harish N. Venkata | 2019-10-08 |
| 10395702 | Memory device with a clocking mechanism | Vijayakrishna J. Vankayala, Todd A. Dauenbaugh | 2019-08-27 |
| 10360959 | Adjusting instruction delays to the latch path in DDR5 DRAM | David D. Wilmoth | 2019-07-23 |
| 10354717 | Reduced shifter memory system | Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda | 2019-07-16 |
| 10275437 | Structured document bounding language | Malcolm H. M. Holloway, Christopher J. Schaubach, Richard S. Szulewski, Lisa M. Bradley | 2019-04-30 |
| 10176858 | Adjusting instruction delays to the latch path in DDR5 DRAM | David D. Wilmoth | 2019-01-08 |
| 9929064 | Through-substrate via (TSV) testing | Venkatraghavan Bringivijayaraghavan | 2018-03-27 |
| 9754224 | Action based to-do list | Lisa M. Bradley, Timothy Brantner, Helen L. Gawor | 2017-09-05 |
| 9542375 | Structured document bounding language | Malcolm H. M. Holloway, Christopher J. Schaubach, Richard S. Szulewski, Lisa M. Wood | 2017-01-10 |
| 9157960 | Through-substrate via (TSV) testing | Venkatraghavan Bringivijayaraghavan | 2015-10-13 |
| 8881762 | System and method implementing air shutoff position detection strategy | Travis S. Johnson, Matthew J. Miller, Michael E. Kenning, Dale E. Koekenberg | 2014-11-11 |
| 8797080 | Circuits, apparatuses, and methods for delay models | Venkatraghavan Bringivijayaraghavan, Tyler Gomm | 2014-08-05 |
| 8767483 | Apparatus and methods having majority bit detection | Venkatraghavan Bringivijayaraghavan | 2014-07-01 |
| 8760961 | Write command and write data timing circuit and methods for timing the same | Venkatraghavan Bringivijayaraghavan | 2014-06-24 |
| 8441888 | Write command and write data timing circuit and methods for timing the same | Venkatraghavan Bringivijayaraghavan | 2013-05-14 |
| 8379469 | Integrated circuit memory operation apparatus and methods | Brian W. Huber | 2013-02-19 |
| 8107305 | Integrated circuit memory operation apparatus and methods | Brian W. Huber | 2012-01-31 |
| 8064269 | Apparatus and methods having majority bit detection | Venkatraghavan Bringivijayaraghavan | 2011-11-22 |
| 8023343 | Systems and methods for issuing address and data signals to a memory array | Venkatraghavan Bringivijayaraghavan | 2011-09-20 |
| 8004313 | Methods, devices, and systems for a high voltage tolerant buffer | Venkatraghavan Bringivijayaraghavan | 2011-08-23 |
| 7969813 | Write command and write data timing circuit and methods for timing the same | Venkatraghavan Bringivijayaraghavan | 2011-06-28 |