Issued Patents All Time
Showing 26–50 of 287 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11862226 | Systems and methods for pre-read scan of memory devices | Karthik Sarpatwari, Nevil N. Gajera, Yen-Chun Lee, Ferdinando Bedeschi | 2024-01-02 |
| 11848051 | Parallel drift cancellation | — | 2023-12-19 |
| 11817148 | Techniques for programming a memory cell | Hernan A. Castro, Innocenzo Tortorelli, Agostino Pirovano | 2023-11-14 |
| 11798620 | Apparatuses including multi-level memory cells and methods of operation of same | Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin | 2023-10-24 |
| 11790987 | Decoding for a memory device | Lorenzo Fratin, Paolo Fantini, Thomas M. Graettinger | 2023-10-17 |
| 11769551 | Multi-level self-selecting memory device | Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano | 2023-09-26 |
| 11765912 | Three dimensional memory arrays | Agostino Pirovano, Andrea Redaelli, Innocenzo Tortorelli | 2023-09-19 |
| 11764146 | Microelectronic devices with self-aligned interconnects, and related methods | Stephen W. Russell, Lorenzo Fratin | 2023-09-19 |
| 11763886 | Techniques to access a self-selecting memory device | Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Mario Allegra, Paolo Fantini | 2023-09-19 |
| 11735261 | Programming enhancement in self-selecting memory | Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli | 2023-08-22 |
| 11729999 | Capacitive pillar architecture for a memory array | Innocenzo Tortorelli | 2023-08-15 |
| 11721394 | Polarity-written cell architectures for a memory device | Agostino Pirovano | 2023-08-08 |
| 11696454 | Three dimensional memory arrays | Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin | 2023-07-04 |
| 11688460 | Memory operation with double-sided asymmetric decoders | Nevil N. Gajera, John F. Schreck | 2023-06-27 |
| 11670367 | Two memory cells sensed to determine one data value | — | 2023-06-06 |
| 11664073 | Adaptively programming memory cells in different modes to optimize performance | Karthik Sarpatwari, Nevil N. Gajera | 2023-05-30 |
| 11647638 | Memory device with double protective liner | Anna Maria Conti, Agostino Pirovano, Kolya Yastrebenetsky | 2023-05-09 |
| 11641788 | Resistive interface material | Andrea Gotti, Dale W. Collins | 2023-05-02 |
| 11616098 | Three-dimensional memory arrays, and methods of forming the same | Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera, Lei Wei | 2023-03-28 |
| 11615854 | Identify the programming mode of memory cells during reading of the memory cells | Karthik Sarpatwari, Nevil N. Gajera | 2023-03-28 |
| 11610634 | Two multi-level memory cells sensed to determine multiple data values | — | 2023-03-21 |
| 11600665 | Cross-point memory and methods for fabrication of same | Marcello Ravasio, Samuele Sciarrillo, Innocenzo Tortorelli, Roberto Somaschini, Cristina Casellato +1 more | 2023-03-07 |
| 11587979 | Three dimensional memory array | Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli | 2023-02-21 |
| 11587606 | Decoding architecture for memory devices | Paolo Fantini, Enrico Varesi, Lorenzo Fratin | 2023-02-21 |
| 11587635 | Selective inhibition of memory | Hongmei Wang, Nevil N. Gajera, Mingdong Cui | 2023-02-21 |