Issued Patents All Time
Showing 51–75 of 287 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11545216 | Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device | Karthik Sarpatwari, Jessica Chen, Nevil N. Gajera | 2023-01-03 |
| 11545625 | Tapered memory cell profiles | Agostino Pirovano, Kolya Yastrebenetsky | 2023-01-03 |
| 11538860 | Memory array with graded memory stack resistances | Lorenzo Fratin, Hongmei Wang | 2022-12-27 |
| 11538513 | Memory element for weight update in a neural network | Karthik Sarpatwari | 2022-12-27 |
| 11515358 | Semiconductor devices including a passive material between memory cells and conductive access lines | Innocenzo Tortorelli | 2022-11-29 |
| 11514983 | Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells | Karthik Sarpatwari, Nevil N. Gajera | 2022-11-29 |
| 11489117 | Self-aligned memory decks in cross-point memory arrays | Agostino Pirovano, Anna Maria Conti, Andrea Redaelli, Innocenzo Tortorelli | 2022-11-01 |
| 11482280 | Apparatuses including multi-level memory cells and methods of operation of same | Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin | 2022-10-25 |
| 11482284 | Parallel drift cancellation | — | 2022-10-25 |
| 11475951 | Material implication operations in memory | Agostino Pirovano | 2022-10-18 |
| 11476304 | Phase change memory device with voltage control elements | Antonino Rigano | 2022-10-18 |
| 11468930 | Vertical decoder | Andrea Redaelli | 2022-10-11 |
| 11430509 | Varying-polarity read operations for polarity-written memory cells | Innocenzo Tortorelli, Hari Giduturi | 2022-08-30 |
| 11423981 | Decoding for a memory device | Paolo Fantini, Lorenzo Fratin | 2022-08-23 |
| 11417841 | Techniques for forming self-aligned memory structures | Stephen W. Russell, Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Lorenzo Fratin | 2022-08-16 |
| 11417394 | Decoding for a memory device | Lorenzo Fratin, Paolo Fantini, Thomas M. Graettinger | 2022-08-16 |
| 11404117 | Self-selecting memory array with horizontal access lines | Lorenzo Fratin, Agostino Pirovano, Russell L. Meyer | 2022-08-02 |
| 11374059 | Memory cells having resistors and formation of the same | Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli | 2022-06-28 |
| 11355554 | Sense lines in three-dimensional memory arrays, and methods of forming the same | Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera, Lei Wei | 2022-06-07 |
| 11342382 | Capacitive pillar architecture for a memory array | Innocenzo Tortorelli | 2022-05-24 |
| 11302393 | Techniques for programming a memory cell | Hernan A. Castro, Innocenzo Tortorelli, Agostino Pirovano | 2022-04-12 |
| 11302390 | Reading a multi-level memory cell | Mattia Robustelli, Innocenzo Tortorelli, Agostino Pirovano | 2022-04-12 |
| 11282895 | Split pillar architectures for memory devices | Paolo Fantini, Lorenzo Fratin | 2022-03-22 |
| 11271153 | Self-selecting memory cell with dielectric barrier | Lorenzo Fratin | 2022-03-08 |
| 11264567 | Memory device with increased electrode resistance to reduce transient selection current | Srivatsan Venkatesan, Davide Mantegazza, John Gorman, Iniyan Soundappa Elango, Davide Fugazza +1 more | 2022-03-01 |