Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11403111 | Reconfigurable processing-in-memory logic using look-up tables | — | 2022-08-02 |
| 11372595 | Read broadcast operations associated with a memory device | Shanky Kumar Jain | 2022-06-28 |
| 11366752 | Address mapping between shared memory modules and cache sets | — | 2022-06-21 |
| 11360704 | Multiplexed signal development in a memory device | Shanky Kumar Jain | 2022-06-14 |
| 11354134 | Processing-in-memory implementations of parsing strings against context-free grammars | — | 2022-06-07 |
| 11355170 | Reconfigurable processing-in-memory logic | — | 2022-06-07 |
| 11340833 | Systems and methods for data relocation using a signal development cache | Shanky Kumar Jain | 2022-05-24 |
| 11334387 | Throttle memory as a service based on connectivity bandwidth | Sean S. Eilert, Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz | 2022-05-17 |
| 11282557 | Magnetic cache for a memory device | — | 2022-03-22 |
| 11276463 | Matching patterns in memory arrays | — | 2022-03-15 |
| 11256624 | Intelligent content migration with borrowed memory | Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean S. Eilert | 2022-02-22 |
| 11232049 | Memory module with computation capability | — | 2022-01-25 |
| 11221797 | Domain-based access in a memory device | Shanky Kumar Jain | 2022-01-11 |
| 11169930 | Fine grain data migration to or from borrowed memory | Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean S. Eilert | 2021-11-09 |
| 11126548 | Accelerated in-memory cache with memory array sections having different configurations | — | 2021-09-21 |
| 11100007 | Memory management unit (MMU) for accessing borrowed memory | Samuel E. Bradshaw, Ameen D. Akel, Kenneth Marion Curewitz, Sean S. Eilert | 2021-08-24 |
| 11061819 | Distributed computing based on memory as a service | Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean S. Eilert | 2021-07-13 |
| 10713059 | Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units | Joseph L. Greathouse, Mitesh R. Meswani, Sooraj Puthoor, James M. O'Connor | 2020-07-14 |
| 10644004 | Utilizing capacitors integrated with memory devices for charge detection to determine DRAM refresh | David A. Roberts | 2020-05-05 |
| 10592279 | Multi-processor apparatus and method of detection and acceleration of lagging tasks | Arkaprava Basu, David A. Roberts, Mitesh R. Meswani, Sergey Blagodurov | 2020-03-17 |
| 10573630 | Offset-aligned three-dimensional integrated circuit | Brett P. Wilkerson, Milind S. Bhagavat, Rahul Agarwal | 2020-02-25 |
| 10529677 | Method and apparatus for power delivery to a die stack via a heat spreader | — | 2020-01-07 |
| 10509596 | Extreme-bandwidth scalable performance-per-watt GPU architecture | Jiasheng Chen | 2019-12-17 |
| 10216454 | Method and apparatus of performing a memory operation in a hierarchical memory assembly | — | 2019-02-26 |
| 10019283 | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread | Sergey Blagodurov, Arkaprava Basu, Sooraj Puthoor, Joseph L. Greathouse | 2018-07-10 |