Brian J. Coppa — 16 Patents at Micron

Brian J. Coppa has been granted 16 US patents while listed as an inventor at Micron. The first was granted in 2012 and the most recent in November 2025. Brian J. Coppa ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Brian J. Coppa in Tempe, AZ, US.

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Showing 1–16 of 16 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12463044	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2025-11-04
12063874	Electrical, mechanical, computing, and/or other devices formed of extremely low resistance materials	Douglas J. Gilbert, Y. Eugene Shteyn, Michael James Smith, Joel Patrick Hanna, Paul Greenland +1 more	2024-08-13
11935756	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2024-03-19
11335563	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2022-05-17	$11,540,000
11289639	Electrical, mechanical, computing, and/or other devices formed of extremely low resistance materials	Douglas J. Gilbert, Y. Eugene Shteyn, Michael James Smith, Joel Patrick Hanna, Paul Greenland +1 more	2022-03-29
11273469	Controlling dry etch process characteristics using waferless dry clean optical emission spectroscopy	Deepak Vedhachalam, Francois C. Dassapa	2022-03-15
10773282	Controlling dry etch process characteristics using waferless dry clean optical emission spectroscopy	Deepak Vedhachalam, Francois C. Dassapa	2020-09-15
10607844	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2020-03-31	$9,822,000
10446453	Surface modification control for etch metric enhancement	Viswas Purohit, Seiichi Watanabe, Kenji Komatsu	2019-10-15
10333047	Electrical, mechanical, computing/ and/or other devices formed of extremely low resistance materials	Douglas J. Gilbert, Y. Eugene Shteyn, Michael James Smith, Joel Patrick Hanna, Paul Greenland +1 more	2019-06-25
10304668	Localized process control using a plasma system	Vaidya Bharadwaj	2019-05-28
10096483	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2018-10-09	$33,519,000
9761457	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2017-09-12	$16,077,000
9305782	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2016-04-05	$6,062,000
8852851	Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same	Baosuo Zhou, Mirzafer Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng +1 more	2014-10-07	$11,727,000
8129289	Method to deposit conformal low temperature SiO2	John Smythe, Gurtej S. Sandhu, Shyam Surthi, Shuang Meng	2012-03-06	$4,847,000

Brian J. Coppa — 16 Patents

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