Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6037639 | Fabrication of integrated devices using nitrogen implantation | — | 2000-03-14 |
| 5946588 | Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides | Randhir P. S. Thakur, J. Brett Rolfson, Brian Benard | 1999-08-31 |
| 5940712 | Method of forming a resistor and integrated circuitry having a resistor construction | Kirk D. Prall, Pierre C. Fazan, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1999-08-17 |
| 5939761 | Method of forming a field effect transistor | Charles H. Dennison | 1999-08-17 |
| 5923078 | Method of forming a resistor and integrated circuitry having a resistor construction | Kirk D. Prall, Pierre C. Fazan, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1999-07-13 |
| 5923977 | Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide | David J. Keller, Tyler Lowrey | 1999-07-13 |
| 5849615 | Semiconductor processing method of fabricating field effect transistors | Kirk D. Prall | 1998-12-15 |
| 5830798 | Method for forming a field effect transistor | Charles H. Dennison | 1998-11-03 |
| 5821150 | Method of forming a resistor and integrated circuitry having a resistor construction | Kirk D. Prall, Pierre C. Fazan, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1998-10-13 |
| 5811329 | Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide | David J. Keller, Tyler Lowrey | 1998-09-22 |
| 5780920 | Method of forming a resistor and integrated circuitry having a resistor construction | Kirk D. Prall, Pierre C. Fazan, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1998-07-14 |
| 5733809 | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells | Charles H. Dennison | 1998-03-31 |
| 5719424 | Graded LDD implant process for sub-half-micron MOS devices | Charles H. Dennison | 1998-02-17 |
| 5716862 | High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS | Randhir P. S. Thakur, Kirk D. Prall, Tyler Lowrey, Brett Rolfson | 1998-02-10 |
| 5702976 | Shallow trench isolation using low dielectric constant insulator | Klaus Schuegraf | 1997-12-30 |
| 5668037 | Method of forming a resistor and integrated circuitry having a resistor construction | Kirk D. Prall, Pierre C. Fazan, Howard E. Rhodes, Werner Juengling, Pai-Hung Pan +1 more | 1997-09-16 |
| 5494841 | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells | Charles H. Dennison | 1996-02-27 |
| 5489546 | Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process | Pierre C. Fazan, Charles H. Dennison | 1996-02-06 |
| 5483175 | Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer | Larren G. Weber, Robert S. Green | 1996-01-09 |
| 5457400 | Semiconductor array having built-in test circuit for wafer level testing | Larren G. Weber, Robert S. Green | 1995-10-10 |
| 5405791 | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers | Tyler Lowrey | 1995-04-11 |
| 5382533 | Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection | Randhir P. S. Thakur | 1995-01-17 |
| 5338700 | Method of forming a bit line over capacitor array of memory cells | Charles H. Dennison | 1994-08-16 |
| 5241266 | Built-in test circuit connection for wafer level burnin and testing of individual dies | Larren G. Weber, Robert S. Green | 1993-08-31 |
| 5208176 | Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization | Pierre C. Fazan, Ruojia Lee | 1993-05-04 |