Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10892265 | Word line structure and method of manufacturing the same | Chi-Min Chen, Yung-Tai Hung, Ta-Hung Yang, Kuang-Chao Chen | 2021-01-12 |
| 10497652 | Semiconductor substrate and semiconductor device | Ling Yang, Ta-Hung Yang, Kuang-Chao Chen | 2019-12-03 |
| 10388664 | Integrated circuit device with layered trench conductors | Yukai Huang, Chun-Ling Chiang, Yung-Tai Hung, Chun-Min Cheng, Ling Yang +2 more | 2019-08-20 |
| 9869712 | Method and system for detecting defects of wafer by wafer sort | I-Jen Huang, Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2018-01-16 |
| 9589086 | Method for measuring and analyzing surface structure of chip or wafer | Hsiang-Chou Liao, Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2017-03-07 |
| 9244112 | Method for detecting an electrical defect of contact/via plugs | Hsiang-Chou Liao, Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2016-01-26 |
| 9116108 | Electron beam inspection optimization | Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2015-08-25 |
| 9006003 | Method of detecting bitmap failure associated with physical coordinate | Chi-Min Chen, Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2015-04-14 |
| 8828861 | Method for fabricating conductive lines of a semiconductor device | Ming-Da Cheng, Chin-Ta Su, Tahone Yang, Kuang-Chao Chen | 2014-09-09 |
| 8669184 | Method for improving flatness of a layer deposited on polycrystalline layer | Ling-Wu Yang, Ta-Hone Yang, Kuang-Chao Chen | 2014-03-11 |
| 8653592 | Isolation structure, non-volatile memory having the same, and method of fabricating the same | Ming-Da Cheng, Chin-Tsan Yeh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2014-02-18 |
| 8594963 | In-line inspection yield prediction system | Hsiang-Chou Liao, Che-Lun Hung, Ling Yang, Ta-Hone Yang, Kuang-Chao Chen | 2013-11-26 |
| 8580680 | Metal silicide formation | Sheng-Hui Hsieh, Ricky Huang, Chin-Ta Su, Tahone Yang, Kuang-Chao Chen | 2013-11-12 |
| 8519541 | Semiconductor device having plural conductive layers disposed within dielectric layer | Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2013-08-27 |
| 8520194 | Method of forming a deposited material by utilizing a multi-step deposition/etch/deposition (D/E/D) process | Sheng-Hui Hsieh, Shing-Ann Luo, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2013-08-27 |
| 8383515 | Methodology for wordline short reduction | Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen | 2013-02-26 |
| 8329480 | Test pattern for detecting piping in a memory array | Che-Lun Hung, Hsiang-Chou Liao, Ling-Wu Yang | 2012-12-11 |
| 8184288 | Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine | Sheng-Hui Hsieh, Shing-Ann Luo, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2012-05-22 |
| 8085390 | Multivariate monitoring method for plasma process machine | Shing-Ann Luo, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2011-12-27 |
| 8067292 | Isolation structure, non-volatile memory having the same, and method of fabricating the same | Ming-Da Cheng, Chin-Tsan Yeh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2011-11-29 |
| 8034691 | HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system | Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen, Shing-Ann Luo | 2011-10-11 |
| 8003519 | Systems and methods for back end of line processing of semiconductor circuits | Chi-Tung Huang, Kuang-Chao Chen, Candy Jiang | 2011-08-23 |
| 7951707 | Etching method for semiconductor element | Ling Yang, Kuang-Chao Chen | 2011-05-31 |
| 7938972 | Fabrication method of electronic device | Ling Yang, Kuang-Chao Chen | 2011-05-10 |
| 7888804 | Method for forming self-aligned contacts and local interconnects simultaneously | Ling Yang, Kuang-Chao Chen | 2011-02-15 |