Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8791022 | Method for reducing wordline bridge rate | Jeng-Hwa Liao, Jung-Yu Shieh | 2014-07-29 |
| 8669184 | Method for improving flatness of a layer deposited on polycrystalline layer | Tuung Luoh, Ta-Hone Yang, Kuang-Chao Chen | 2014-03-11 |
| 8581327 | Memory and manufacturing method thereof | Erh-Kun Lai, Yen-Hao Shih, Chun-Min Cheng | 2013-11-12 |
| 8383515 | Methodology for wordline short reduction | Tuung Luoh, Tahone Yang, Kuang-Chao Chen | 2013-02-26 |
| 8329480 | Test pattern for detecting piping in a memory array | Che-Lun Hung, Hsiang-Chou Liao, Tuung Luoh | 2012-12-11 |
| 8288280 | Conductor removal process | Yung-Tai Hung, Chin-Tsan Yeh, Chin-Ta Su, Tung-Han Chuang | 2012-10-16 |
| 8211806 | Method of fabricating integrated circuit with small pitch | Chia-Wei Wu | 2012-07-03 |
| 8106483 | Wafer with improved intrinsic gettering ability | Chun-Ling Chiang, Jung-Yu Hsieh | 2012-01-31 |
| 7939432 | Method of improving intrinsic gettering ability of wafer | Chun-Ling Chiang, Jung-Yu Hsieh | 2011-05-10 |
| 7879706 | Memory and manufacturing method thereof | Erh-Kun Lai, Yen-Hao Shih, Chun-Min Cheng | 2011-02-01 |
| 7776713 | Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation | Chia-Wei Wu, Jung-Yu Shieh | 2010-08-17 |
| 7625819 | Interconnection process | Tuung Luoh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen | 2009-12-01 |
| 7544616 | Methods of forming nitride read only memory and word lines thereof | Chi-Pin Lu | 2009-06-09 |