Issued Patents All Time
Showing 151–175 of 175 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492235 | Method for forming extension by using double etch spacer | Han-Chao Lai, Hung-Sui Lin | 2002-12-10 |
| 6482709 | Manufacturing process of a MOS transistor | Han-Chao Lai, Hung-Sui Lin | 2002-11-19 |
| 6482706 | Method to scale down device dimension using spacer to confine buried drain implant | Yen-Hung Yeh, Tso-Hung Fan, Mu-Yi Liu, Kwang-Yang Chan | 2002-11-19 |
| 6465849 | CMOS structure having dynamic threshold voltage | Yao-Wen Chang | 2002-10-15 |
| 6458642 | Method of fabricating a sonos device | Yen-Hung Yeh, Tso-Hung Fan, Mu-Yi Liu, Kwang-Yang Chan | 2002-10-01 |
| 6458643 | Method of fabricating a MOS device with an ultra-shallow junction | Han-Chao Lai, Hung-Sui Lin | 2002-10-01 |
| 6455376 | Method of fabricating flash memory with shallow and deep junctions | Tso-Hung Fan, Wen-Jer Tsai | 2002-09-24 |
| 6455388 | Method of manufacturing metal-oxide semiconductor transistor | Han-Chao Lai, Hung-Sui Lin | 2002-09-24 |
| 6455898 | Electrostatic discharge input protection for reducing input resistance | Meng-Hwang Liu, Mam-Tsung Wang | 2002-09-24 |
| 6448142 | Method for fabricating a metal oxide semiconductor transistor | Han-Chao Lai, Hung-Sui Lin | 2002-09-10 |
| 6444523 | Method for fabricating a memory device with a floating gate | Tso-Hung Fan, Wen-Jer Tsai, Samuel C. Pan | 2002-09-03 |
| 6432782 | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate | Hsing Lan Lung, Mam-Tsung Wang | 2002-08-13 |
| 6410963 | Electrostatic discharge protection circuits with latch-up prevention function | Chen-Shang Lai, Meng-Huang Liu, Shin Su | 2002-06-25 |
| 6320786 | Method of controlling multi-state NROM | Yao-Wen Chang, Wen-Jer Tsai | 2001-11-20 |
| 6269017 | Multi level mask ROM with single current path | Chung-Ju Chen, Mam-Tsung Wang | 2001-07-31 |
| 6259140 | Silicide blocking process to form non-silicided regions on MOS devices | Meng-Hwang Liu, Cheng-Shang Lai, Mam-Tsung Wang | 2001-07-10 |
| 6215697 | Multi-level memory cell device and method for self-converged programming | Der-Shin Shyu, Shi-Xian Chen, Wen-Jer Tsai, Mam-Tsung Wang | 2001-04-10 |
| 6204529 | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate | Hsing Lan Lung, Mam-Tsung Wang | 2001-03-20 |
| 6181604 | Method for fast programming of EPROMS and multi-level flash EPROMS | Wen-Jer Tsai, Mam-Tsung Wang, Chin-Hsi Lin, Ful-Long Ni | 2001-01-30 |
| 6175519 | Virtual ground EPROM structure | Mam-Tsung Wang, Chin-Hsi Lin, Ful-Long Ni | 2001-01-16 |
| 6140682 | Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage | Meng-Hwang Liu, Chen-Shang Lai, Mam-Tsung Wang | 2000-10-31 |
| 6121092 | Silicide blocking process to form non-silicided regions on MOS devices | Meng-Hwang Liu, Cheng-Shang Lai, Mam-Tsung Wang | 2000-09-19 |
| 6046482 | Cell structure for mask ROM | Mam-Tsung Wang | 2000-04-04 |
| 5963808 | Method of forming an asymmetric bird's beak cell for a flash EEPROM | Wenpin Lu, Mam-Tsung Wang | 1999-10-05 |
| 5895241 | Method for fabricating a cell structure for mask ROM | Mam-Tsung Wang | 1999-04-20 |