Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5654210 | Process for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrate | James Kimball | 1997-08-05 |
| 5585286 | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device | James Kimball, Yu-Lam Ho, Gobi R. Padmanabhan, Douglas T. Grider, Chi-Yi Kao | 1996-12-17 |
| 5571744 | Defect free CMOS process | Esin Kutlu Demirlioglu | 1996-11-05 |
| 5538907 | Method for forming a CMOS integrated circuit with electrostatic discharge protection | Rosario Consiglio, Abraham Yee | 1996-07-23 |
| 5508211 | Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate | Abraham Yee | 1996-04-16 |
| 5504016 | Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions | — | 1996-04-02 |
| 5468974 | Control and modification of dopant distribution and activation in polysilicon | Yen-Hui Ku, Yu-Lam Ho | 1995-11-21 |
| 5459085 | Gate array layout to accommodate multi angle ion implantation | Nicholas F. Pasen, Aldona M. Butkus | 1995-10-17 |
| 5453389 | Defect-free bipolar process | Robert J. Strain | 1995-09-26 |
| 5441900 | CMOS latchup suppression by localized minority carrier lifetime reduction | Constantin Bulucea, Esin Dermirlioglu | 1995-08-15 |
| 5384477 | CMOS latchup suppression by localized minority carrier lifetime reduction | Constantin Bulucea, Esin Dermirlioglu | 1995-01-24 |
| 5376560 | Method for forming isolated semiconductor structures | Courtney L. Hart | 1994-12-27 |
| 5372952 | Method for forming isolated semiconductor structures | Courtney L. Hart | 1994-12-13 |
| 5357135 | Dmost junction breakdown enhancement | George P. Walker, Peter P. Meng, Farrokh Mohammadi, Bhaskar V. S. Gadepally | 1994-10-18 |
| 5312766 | Method of providing lower contact resistance in MOS transistors | Courtney L. Hart, Court Skinner | 1994-05-17 |
| 5298435 | Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon | Courtney L. Hart, Sung Tae Ahn | 1994-03-29 |
| 5296387 | Method of providing lower contact resistance in MOS transistor structures | Courtney L. Hart | 1994-03-22 |
| 5296386 | Method of providing lower contact resistance in MOS transistor structures | Courtney L. Hart, Court Skinner | 1994-03-22 |
| 5292402 | Masking material for applications in plasma etching | Norman E. Abt | 1994-03-08 |
| 5280185 | Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon | Courtney L. Hart, Sung Tae Ahn | 1994-01-18 |
| 5192712 | Control and moderation of aluminum in silicon using germanium and germanium with boron | Amolak R. Ramde | 1993-03-09 |
| 5137838 | Method of fabricating P-buried layers for PNP devices | Amolak R. Ramde | 1992-08-11 |
| 5095358 | Application of electronic properties of germanium to inhibit N-type or P-type diffusion in silicon | Courtney L. Hart, Sung Tae Ahn | 1992-03-10 |
| 5043292 | Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures | Courtney L. Hart, Matthew S. Buynoski | 1991-08-27 |
| 4985717 | MOS memory cell with exponentially-profiled doping and offset floating gate tunnel oxidation | Donald D. Forsythe, George P. Walker, Bhaskar V. S. Gadepally | 1991-01-15 |