Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8304780 | Printed dopant layers | James M. Cleeves, Joerg Rockenberger, Patrick Smith, Fabio R. Zurcher | 2012-11-06 |
| 8296943 | Method for making surveillance devices with multiple capacitors | Patrick Smith, Criswell Choi, James M. Cleeves, Vivek Subramanian, Steven Molesa | 2012-10-30 |
| 8264027 | Printed non-volatile memory | Patrick Smith, James M. Cleeves | 2012-09-11 |
| 8264359 | High reliability surveillance and/or identification tag/devices and methods of making and using the same | Vivek Subramanian, Patrick Smith, Vikram Pavate, Criswell Choi, Aditi Chandra +1 more | 2012-09-11 |
| 8227320 | High reliability surveillance and/or identification tag/devices and methods of making and using the same | Vivek Subramanian, Patrick Smith, Vikram Pavate, Criswell Choi, Aditi Chandra +1 more | 2012-07-24 |
| 8158518 | Methods of making metal silicide contacts, interconnects, and/or seed layers | Aditi Chandra, James M. Cleeves, Joerg Rockenberger, Mao Takashima, Erik C. Scher | 2012-04-17 |
| 8021955 | Method characterizing materials for a trench isolation structure having low trench parasitic capacitance | Venkatesh P. Gopinath, Mohammad Mirabedini, Ming-Yi Lee | 2011-09-20 |
| 7767520 | Printed dopant layers | James M. Cleeves, Joerg Rockenberger, Patrick Smith, Fabio R. Zurcher | 2010-08-03 |
| 7709307 | Printed non-volatile memory | Patrick Smith, James M. Cleeves | 2010-05-04 |
| 7701011 | Printed dopant layers | James M. Cleeves, Joerg Rockenberger, Patrick Smith, Fabio R. Zurcher | 2010-04-20 |
| 7687327 | Methods for manufacturing RFID tags and structures formed therefrom | James M. Cleeves, J. Devin MacKenzie | 2010-03-30 |
| 7619294 | Shallow trench isolation structure with low trench parasitic capacitance | Venkatesh P. Gopinath, Mohammad Mirabedini, Ming-Yi Lee | 2009-11-17 |
| 7413996 | High k gate insulator removal | Wai Lo, Venkatesh P. Gopinath | 2008-08-19 |
| 7026217 | Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate | Venkatesh P. Gopinath, Wen-Chin Yeh, David William PACHURA | 2006-04-11 |
| 7001823 | Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance | Venkatesh P. Gopinath, Mohammad Mirabedini, Ming-Yi Lee | 2006-02-21 |
| 6989331 | Hard mask removal | Venkatesh P. Gopinath, Mohammad Mirabedini, Ming-Yi Lee, Brian A. Baylis | 2006-01-24 |
| 6949446 | Method of shallow trench isolation formation and planarization | Venkatesh P. Gopinth | 2005-09-27 |
| 6812158 | Modular growth of multiple gate oxides | Wen-Chin Yeh, Venkatesh P. Gopinath | 2004-11-02 |
| 6687114 | High density memory with storage capacitor | Ruggero Castagnetti | 2004-02-03 |
| 6680243 | Shallow junction formation | Rajiv Patel | 2004-01-20 |
| 6656805 | METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT | Rajiv Patel, Ravindra M. Kapre | 2003-12-02 |
| 6617251 | Method of shallow trench isolation formation and planarization | Venkatesh P. Gopinth | 2003-09-09 |
| 6586814 | Etch resistant shallow trench isolation in a semiconductor wafer | Rajiv Patel, David Chan, Ken Rafftesaeth, Venkatesh P. Gopinath | 2003-07-01 |
| 6586291 | High density memory with storage capacitor | Ruggero Castagnetti | 2003-07-01 |
| 6569739 | Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers | Venkatesh P. Gopinath | 2003-05-27 |