Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8277675 | Method of damaged low-k dielectric film layer removal | Seokmin Yun, Seong Hwan Cho, Mark Wilcoxson, John M. de Larios, Stephan Hoffmann | 2012-10-02 |
| 8211238 | System, method and apparatus for self-cleaning dry etch | Andrew D. Bailey, III, Arthur M. Howald, Yunsang Kim | 2012-07-03 |
| 8017516 | Method for stress free conductor removal | Andrew D. Bailey, III | 2011-09-13 |
| 7959984 | Methods and arrangement for the reduction of byproduct deposition in a plasma processing system | Andrew D. Bailey, III | 2011-06-14 |
| 7413673 | Method for adjusting voltage on a powered Faraday shield | Andras Kuthi, Andrew D. Bailey, III | 2008-08-19 |
| 7380982 | Accurate temperature measurement for semiconductor applications | — | 2008-06-03 |
| 7232766 | System and method for surface reduction, passivation, corrosion prevention and activation of copper surface | Andrew D. Bailey, III | 2007-06-19 |
| 7217649 | System and method for stress free conductor removal | Andrew D. Bailey, III | 2007-05-15 |
| 7140374 | System, method and apparatus for self-cleaning dry etch | Andrew D. Bailey, III, Arthur M. Howald, Yunsang Kim | 2006-11-28 |
| 7129167 | Methods and systems for a stress-free cleaning a surface of a substrate | Andrew D. Bailey, III, Yunsang Kim, Simon McClatchie | 2006-10-31 |
| 6939796 | System, method and apparatus for improved global dual-damascene planarization | Andrew D. Bailey, III, David Hemker, Joel M. Cook | 2005-09-06 |
| 6821899 | System, method and apparatus for improved local dual-damascene planarization | Andrew D. Bailey, III, David Hemker, Joel M. Cook | 2004-11-23 |