Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9673329 | Method for manufacturing a fin MOS transistor | Yves Morand, Romain Wacquez, Laurent Grenouillet, Maud Vinet | 2017-06-06 |
| 9601511 | Low leakage dual STI integrated circuit including FDSOI transistors | Maud Vinet, Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz +1 more | 2017-03-21 |
| 9570465 | Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same | Maud Vinet, Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz +1 more | 2017-02-14 |
| 9437474 | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions | Laurent Grenouillet, Nicolas Loubet, Maud Vinet, Romain Wacquez | 2016-09-06 |
| 9373507 | Defective P-N junction for backgated fully depleted silicon on insulator mosfet | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Qing Liu +1 more | 2016-06-21 |
| 9337350 | Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same | Nicolas Posseme, Laurent Grenouillet, Maud Vinet | 2016-05-10 |
| 9293474 | Dual channel hybrid semiconductor-on-insulator semiconductor devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Laurent Grenouillet +1 more | 2016-03-22 |
| 9236478 | Method for manufacturing a fin MOS transistor | Yves Morand, Romain Wacquez, Laurent Grenouillet, Maud Vinet | 2016-01-12 |
| 9231062 | Method for treating the surface of a silicon substrate | Laurent Grenouillet, Maud Vinet, Romain Wacquez | 2016-01-05 |
| 9214515 | Method for making a semiconductor structure with a buried ground plane | Francois Andrieu | 2015-12-15 |
| 9105691 | Contact isolation scheme for thin buried oxide substrate devices | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Qing Liu +1 more | 2015-08-11 |
| 9076732 | Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer | Laurent Grenouillet, Nicolas Posseme, Maud Vinet | 2015-07-07 |
| 9070709 | Method for producing a field effect transistor with implantation through the spacers | Nicolas Posseme, Laurent Grenouillet, Nicolas Loubet, Maud Vinet | 2015-06-30 |
| 9059041 | Dual channel hybrid semiconductor-on-insulator semiconductor devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Laurent Grenouillet +1 more | 2015-06-16 |
| 8994142 | Field effect transistor with offset counter-electrode contact | Maud Vinet, Laurent Grenouillet, Nicolas Posseme | 2015-03-31 |
| 8987854 | Microelectronic device with isolation trenches extending under an active area | Maud Vinet, Laurent Grenouillet, Romain Wacquez | 2015-03-24 |
| 8969966 | Defective P-N junction for backgated fully depleted silicon on insulator MOSFET | Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Qing Liu +1 more | 2015-03-03 |
| 8877618 | Method for producing a field effect transistor with a SiGe channel by ion implantation | Laurent Grenouillet, Maud Vinet, Romain Wacquez, Olivier Faynot | 2014-11-04 |
| 8735259 | Method of producing insulation trenches in a semiconductor on insulator substrate | Laurent Grenouillet, Maud Vinet | 2014-05-27 |
| 8722499 | Method for fabricating a field effect device with weak junction capacitance | Maud Vinet, Laurent Grenouillet, Nicolas Posseme | 2014-05-13 |
| 8530331 | Process for assembling substrates with low-temperature heat treatments | Remi Beneyton, Hubert Moriceau, Frank Fournel, Francois Rieutord | 2013-09-10 |
| 8501588 | Method for making a semiconductor structure with a buried ground plane | Francois Andrieu | 2013-08-06 |