YR

Yogendra Ranade

Lsi Logic: 4 patents #471 of 1,957Top 25%
Overall (All Time): #1,250,882 of 4,157,543Top 35%
4
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7354790 Method and apparatus for avoiding dicing chip-outs in integrated circuit die Parthasarathy Rajagopalan, Zafer Kutlu, Emery Sugasawara, Charles E. VONDERACH, Dilip Vijay +2 more 2008-04-08
7145232 Construction to improve thermal performance and reduce die backside warpage Rajagopalan Parthasarathy, Kishore Desai 2006-12-05
6825066 Stiffener design Anand Govind, Kumar Nagarajan, Farshad Ghahghahi, Aritharan Thurairajaratnam 2004-11-30
6759921 Characteristic impedance equalizer and an integrated circuit package employing the same Anand Govind 2004-07-06