CV

Charles E. VONDERACH

Lsi Logic: 1 patents #1,146 of 1,957Top 60%
Overall (All Time): #3,352,737 of 4,157,543Top 85%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7354790 Method and apparatus for avoiding dicing chip-outs in integrated circuit die Parthasarathy Rajagopalan, Zafer Kutlu, Emery Sugasawara, Dilip Vijay, Yogendra Ranade +2 more 2008-04-08