Issued Patents All Time
Showing 25 most recent of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11921565 | Load adjusted populations of integrated circuit decoupling capacitors | Vlad Radu CALUGARU | 2024-03-05 |
| 11710726 | Through-board power control arrangements for integrated circuit devices | Gregory M. Daly, Rich Tat An, Andres Felipe Hernandez Mojica, Garrett Douglas Blankenburg | 2023-07-25 |
| 11209886 | Clock frequency adjustment for workload changes in integrated circuit devices | Andrew Benson Maki, Francine Mary Shammami | 2021-12-28 |
| 11105844 | Predictive voltage transient reduction in integrated circuits | Gregory M. Daly, Rich Tat An, Andres Felipe Hernandez Mojica, Garrett Douglas Blankenburg | 2021-08-31 |
| 11093019 | Integrated circuit power domains segregated among power supply phases | Steven William RANTA, Andres Felipe Hernandez Mojica | 2021-08-17 |
| 11016551 | Thermal rotation of power supply phases | Steven William RANTA, Andres Felipe Hernandez Mojica, Rich Tat An, Garrett Douglas Blankenburg | 2021-05-25 |
| 11010330 | Integrated circuit operation adjustment using redundant elements | Peter Atkinson, Robert James Ray, Garrett Douglas Blankenburg, Andres Hernandez | 2021-05-18 |
| 10928885 | Processor device supply voltage characterization | Garrett Douglas Blankenburg, Peter Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad +2 more | 2021-02-23 |
| 10755020 | Thermal arrangement of modules in server assemblies | Andres Felipe Hernandez Mojica, Garrett Douglas Blankenburg | 2020-08-25 |
| 10503231 | Load line regulation via clamping voltage | Peter Atkinson, Steven William RANTA, Francine Mary Shammami | 2019-12-10 |
| 10338670 | Input voltage reduction for processing devices | Garrett Douglas Blankenburg, Peter Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad +2 more | 2019-07-02 |
| 10310572 | Voltage based thermal control of processing device | Garrett Douglas Blankenburg, Peter Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad +2 more | 2019-06-04 |
| 10268248 | Power based thermal management of device | Andres Hernandez, Peter Atkinson, Gregory M. Daly, Garrett Douglas Blankenburg | 2019-04-23 |
| 10248186 | Processor device voltage characterization | Garrett Douglas Blankenburg, Peter Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad +2 more | 2019-04-02 |
| 10209726 | Secure input voltage adjustment in processing devices | Garrett Douglas Blankenburg, Peter Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad +2 more | 2019-02-19 |
| 10096353 | System and memory controller for interruptible memory refresh | Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow +1 more | 2018-10-09 |
| 9972376 | Memory device for interruptible memory refresh | Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow +1 more | 2018-05-15 |
| 9612988 | Donor cores to improve integrated circuit yield | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann | 2017-04-04 |
| 9568940 | Multiple active vertically aligned cores for three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker | 2017-02-14 |
| 9383767 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, Kirk D. Peterson, Mack W. Riley | 2016-07-05 |
| 9312199 | Intelligent chip placement within a three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann | 2016-04-12 |
| 9310827 | Multiple active vertically aligned cores for three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker | 2016-04-12 |
| 9281261 | Intelligent chip placement within a three-dimensional chip stack | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann | 2016-03-08 |
| 9250645 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, Kirk D. Peterson, Mack W. Riley | 2016-02-02 |
| 9207275 | Interconnect solder bumps for die testing | Gerald K. Bartley, Philip Raymond Germann | 2015-12-08 |