Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11899615 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2024-02-13 |
| 11586579 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2023-02-21 |
| 11354264 | Bimodal PHY for low latency in high speed interconnects | Venkatraman Iyer, Rahul R. Shah, Eric M. Lee | 2022-06-07 |
| 11294852 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2022-04-05 |
| 10963415 | Bimodal PHY for low latency in high speed interconnects | Venkatraman Iyer, Rahul R. Shah, Eric M. Lee | 2021-03-30 |
| 10931329 | High speed interconnect with channel extension | Rahul R. Shah, Fulvio Spagna, Venkatraman Iyer | 2021-02-23 |
| 10795853 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more | 2020-10-06 |
| 10599602 | Bimodal phy for low latency in high speed interconnects | Venkatraman Iyer, Rahul R. Shah, Eric M. Lee | 2020-03-24 |
| 10372657 | Bimodal PHY for low latency in high speed interconnects | Venkatraman Iyer, Rahul R. Shah, Eric M. Lee | 2019-08-06 |
| 10324882 | High performance interconnect link state transitions | Rahul R. Shah, Venkatraman Iyer | 2019-06-18 |
| 10152446 | Link-physical layer interface adapter | Venkatraman Iyer, Mahesh Wagh, Rahul R. Shah | 2018-12-11 |
| 10025746 | High performance interconnect | Rahul R. Shah, Venkatraman Iyer | 2018-07-17 |
| 9910809 | High performance interconnect link state transitions | Rahul R. Shah, Venkatraman Iyer | 2018-03-06 |
| 8135869 | Task scheduling to devices with same connection address | Naichih Chang, Victor Lau, Pak-Lung Seto | 2012-03-13 |
| 7797463 | Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications | Pak-Lung Seto, Victor Lau, Naichih Chang | 2010-09-14 |
| 7676604 | Task context direct indexing in a protocol engine | Victor Lau, Pak-Lung Seto, Naichih Chang | 2010-03-09 |
| 7664889 | DMA descriptor management mechanism | Kiran Vemula, Pak-Iung Seto, Victor Lau, Nai-Chih Chang | 2010-02-16 |
| 7506080 | Parallel processing of frame based data transfers | Victor Lau, Pak-Lung Seto, Suresh Chemudupati, Naichih Chang | 2009-03-17 |
| 7415549 | DMA completion processing mechanism | Kiran Vemula, Victor Lau, Pak-Lung Seto, Nai-Chih Chang, Suresh Chemudupati +2 more | 2008-08-19 |
| 7376789 | Wide-port context cache apparatus, systems, and methods | Pak-Lung Seto, Victor Lau | 2008-05-20 |