Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9864711 | Automatic downstream to upstream mode switching at a universal serial bus physical layer | Jennifer Wang, Alejandro Lenero Beracoechea, Steven B. McGowan | 2018-01-09 |
| 8626979 | Common protocol engine interface for a controller interface | Jennifer Wang, Beracoecha Alejandro Lenero, Yew Kee Wong | 2014-01-07 |
| 8539131 | Root hub virtual transaction translator | Jennifer Wang, Alejandro Lenero Beracoechea | 2013-09-17 |
| 8112507 | Remote node list searching mechanism for storage task scheduling | Pak-Lung Seto | 2012-02-07 |
| 7984208 | Method using port task scheduler | Tracey L. Gustafson, Pak-Lung Seto, Gary Tsao, Victor Lau | 2011-07-19 |
| 7664889 | DMA descriptor management mechanism | Kiran Vemula, Pak-Iung Seto, Victor Lau, William R. Halleck | 2010-02-16 |
| 7620751 | Command scheduling and affiliation management for serial attached storage devices | Victor Lau, Pak-Lung Seto | 2009-11-17 |
| 7516257 | Mechanism to handle uncorrectable write data errors | Victor Lau, Pak-Lung Seto | 2009-04-07 |
| 7451255 | Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support | Tracey L. Gustafson, Pak-Lung Seto, Gary Tsao, Victor Lau | 2008-11-11 |
| 7450588 | Storage network out of order packet reordering mechanism | Pak-Lung Seto | 2008-11-11 |
| 7418615 | Universal timeout mechanism | Pak-Iung Seto, Victor Lau | 2008-08-26 |
| 7415549 | DMA completion processing mechanism | Kiran Vemula, Victor Lau, Pak-Lung Seto, William R. Halleck, Suresh Chemudupati +2 more | 2008-08-19 |
| 7366817 | Frame order processing apparatus, systems, and methods | Pak-Lung Seto, Victor Lau | 2008-04-29 |
| 7221531 | Staggered spin-up disable mechanism | Vicky Duerk, Pak-Lung Seto, Victor Lau | 2007-05-22 |