| 9298867 |
Modular system and method for simulating performance of an electrical device |
Hector A. Valerio, Nathaniel Jennings, Nicole Taylor Gonzalez |
2016-03-29 |
$10,406,000 |
| 8370581 |
System and method for dynamic data prefetching |
Pak-Lung Seto, Eric J. Dehaemer |
2013-02-05 |
$13,504,000 |
| 8149854 |
Multi-threaded transmit transport engine for storage devices |
Pak-Lung Seto |
2012-04-03 |
$17,954,000 |
| 8135869 |
Task scheduling to devices with same connection address |
Naichih Chang, Pak-Lung Seto, William R. Halleck |
2012-03-13 |
$53,474,000 |
| 8032675 |
Dynamic memory buffer allocation method and system |
Naichih Chang, Pak-Lung Seto |
2011-10-04 |
$13,316,000 |
| 7984208 |
Method using port task scheduler |
Tracey L. Gustafson, Pak-Lung Seto, Gary Tsao, Nai-Chih Chang |
2011-07-19 |
$15,862,000 |
| 7970953 |
Serial ATA port addressing |
Naichih Chang, Pak-Iung Seto, Luke Chang |
2011-06-28 |
$18,630,000 |
| 7805543 |
Hardware oriented host-side native command queuing tag management |
Naichih Chang, Pak-Lung Seto |
2010-09-28 |
$14,170,000 |
| 7797463 |
Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications |
William R. Halleck, Pak-Lung Seto, Naichih Chang |
2010-09-14 |
$15,475,000 |
| 7747788 |
Hardware oriented target-side native command queuing tag management |
Naichih Chang, Pak-Lung Seto |
2010-06-29 |
$12,144,000 |
| 7730239 |
Data buffer management in a resource limited environment |
Naichih Chang, Pak-Lung Seto |
2010-06-01 |
$13,475,000 |
| 7676604 |
Task context direct indexing in a protocol engine |
William R. Halleck, Pak-Lung Seto, Naichih Chang |
2010-03-09 |
$23,050,000 |
| 7664889 |
DMA descriptor management mechanism |
Kiran Vemula, Pak-Iung Seto, William R. Halleck, Nai-Chih Chang |
2010-02-16 |
$21,778,000 |
| 7620751 |
Command scheduling and affiliation management for serial attached storage devices |
Nai-Chih Chang, Pak-Lung Seto |
2009-11-17 |
$26,173,000 |
| 7516257 |
Mechanism to handle uncorrectable write data errors |
Pak-Lung Seto, Nai-Chih Chang |
2009-04-07 |
$17,723,000 |
| 7506080 |
Parallel processing of frame based data transfers |
Pak-Lung Seto, Suresh Chemudupati, Naichih Chang, William R. Halleck |
2009-03-17 |
|
| 7480832 |
Centralized error signaling and logging |
Suresh Chemudupati, Bruno DiPlacido, Eric J. Dehaemer |
2009-01-20 |
$15,289,000 |
| 7451255 |
Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support |
Tracey L. Gustafson, Pak-Lung Seto, Gary Tsao, Nai-Chih Chang |
2008-11-11 |
$15,138,000 |
| 7418615 |
Universal timeout mechanism |
Nai-Chih Chang, Pak-Iung Seto |
2008-08-26 |
$24,347,000 |
| 7415549 |
DMA completion processing mechanism |
Kiran Vemula, Pak-Lung Seto, Nai-Chih Chang, William R. Halleck, Suresh Chemudupati +2 more |
2008-08-19 |
$22,118,000 |
| 7376789 |
Wide-port context cache apparatus, systems, and methods |
William R. Halleck, Pak-Lung Seto |
2008-05-20 |
$25,766,000 |
| 7366817 |
Frame order processing apparatus, systems, and methods |
Nai-Chih Chang, Pak-Lung Seto |
2008-04-29 |
$13,885,000 |
| 7221531 |
Staggered spin-up disable mechanism |
Vicky Duerk, Nai-Chih Chang, Pak-Lung Seto |
2007-05-22 |
$18,006,000 |
