Issued Patents All Time
Showing 25 most recent of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10186482 | Self aligned via fuse | Junjing Bao, Samuel S. Choi | 2019-01-22 |
| 10049926 | Metal lines having etch-bias independent height | Junjing Bao | 2018-08-14 |
| 10032794 | Bridging local semiconductor interconnects | Chieh-Yu Lin, Yannick Daurelle | 2018-07-24 |
| 9960226 | High density capacitor structure and method | Chengwen Pei, Ping-Chuan Wang | 2018-05-01 |
| 9859303 | Bridging local semiconductor interconnects | Chieh-Yu Lin, Yannick Daurelle | 2018-01-02 |
| 9768110 | Physical unclonable interconnect function array | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2017-09-19 |
| 9755016 | Integration process to form microelectronic or micromechanical structures | Samuel S. Choi | 2017-09-05 |
| 9755013 | High density capacitor structure and method | Chengwen Pei, Ping-Chuan Wang | 2017-09-05 |
| 9691718 | On-chip semiconductor device having enhanced variability | Chengwen Pei, Ping-Chuan Wang | 2017-06-27 |
| 9666582 | On-chip finFET structures to implement physical unclonable function for security application | Chengwen Pei | 2017-05-30 |
| 9627272 | Patterning scheme to minimize dry/wets strip induced device degradation | Huihang Dong | 2017-04-18 |
| 9576914 | Inducing device variation for security applications | Chengwen Pei, Ping-Chuan Wang | 2017-02-21 |
| 9515148 | Bridging local semiconductor interconnects | Chieh-Yu Lin, Yannick Daurelle | 2016-12-06 |
| 9472463 | Patterning process for Fin implantation | Huihang Dong | 2016-10-18 |
| 9465290 | Near-infrared absorbing film compositions | Wu-Song Huang, Martin Glodde, Dario L. Goldfarb, Sen Liu, Libor Vyklicky | 2016-10-11 |
| 9449822 | Method of forming semiconductor structures with contact holes | Wu-Song Huang, Joy Cheng, Kuang-Jung Chen | 2016-09-20 |
| 9443770 | Patterning process for fin implantation | Huihang Dong | 2016-09-13 |
| 9391014 | Physical unclonable interconnect function array | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2016-07-12 |
| 9391030 | On-chip semiconductor device having enhanced variability | Chengwen Pei, Ping-Chuan Wang | 2016-07-12 |
| 9337261 | Method of forming microelectronic or micromechanical structures | Samuel S. Choi | 2016-05-10 |
| 9337082 | Metal lines having etch-bias independent height | Junjing Bao | 2016-05-10 |
| 9331012 | Method for fabricating a physical unclonable interconnect function array | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2016-05-03 |
| 9316916 | Method to mitigate resist pattern critical dimension variation in a double-exposure process | Kuang-Jung Chen, Wu-Song Huang | 2016-04-19 |
| 9312366 | Processing of integrated circuit for metal gate replacement | Huihang Dong | 2016-04-12 |
| 9312191 | Block patterning process for post fin | — | 2016-04-12 |