Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6534393 | Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity | Mei Sheng Zhou, Jian Xun Li | 2003-03-18 |
| 6391732 | Method to form self-aligned, L-shaped sidewall spacers | Subhash Gupta, Yelehanka Ramachandramurthy | 2002-05-21 |
| 6387765 | Method for forming an extended metal gate using a damascene process | Yelehanka Ramachandramurthy Pradeep, Mei Sheng Zhou, Henry Gerung, Simon Chooi | 2002-05-14 |
| 6337262 | Self aligned T-top gate process integration | Yelehanka Ramachandramurthy Pradeep, Chivukula Subrahmanyam, Henry Gerung | 2002-01-08 |
| 6249035 | LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect | Igor Peidous, Quek Kiok Boone Elgin, Konstantin V. Loiko, Tan Poh Suan | 2001-06-19 |
| 6228770 | Method to form self-sealing air gaps between metal interconnects | Yelehanka Ramachandramurthy Pradeep, Henry Gerung, Madhusudan Mukhopadhyay | 2001-05-08 |
| 6071793 | Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect | Igor Peidous, Quek Kiok Boone Elgin, Konstantin V. Loiko, Tan Poh Suan | 2000-06-06 |