Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8042078 | Enhancing formal design verification by reusing previous results | Viresh Paruthi, Mark A. Williams | 2011-10-18 |
| 7979732 | Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit | Lawrence D. Curley, John M. Isakson, Arjen A. Mets, Thomas E. Rosser, Kristen Tucker | 2011-07-12 |
| 7979838 | Method of automating creation of a clock control distribution network in an integrated circuit floorplan | Christopher J. Berry, Jose L. Neves, Lawrence D. Curley, Patrick J. Meaney, William J. Scarpero, Jr. | 2011-07-12 |
| 7546561 | System and method of state point correspondence with constrained function determination | Viresh Paruthi | 2009-06-09 |