Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6899241 | Waste collecting box | — | 2005-05-31 |
| 6514441 | Radial tire manufacturing method | Yukio Saegusa | 2003-02-04 |
| 6510456 | Data transfer control method and system, data transfer control program file, and file storage medium | Naoko Ikegaya, Taketoshi Sakuraba | 2003-01-21 |
| 6321260 | Media data communication method via network | Tadashi Takeuchi, Takahiro Nakano, Masaaki Iwasaki | 2001-11-20 |
| 6298355 | Computer system | Tadayuki Sakakibara, Hiromitsu Maeda | 2001-10-02 |
| 5892923 | Parallel computer system using properties of messages to route them through an interconnect network and to select virtual channel circuits therewithin | Yoshiko Yasuda | 1999-04-06 |
| 5857110 | Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors | Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto, Yasuhiro Inagami +1 more | 1999-01-05 |
| 5826049 | Partial broadcast method in parallel computer and a parallel computer suitable therefor | Yasuhiro Ogata, Junji Nakagoshi, Naoki Hamanaka, Hiroyuki Chiba, Shinichi Shutoh +3 more | 1998-10-20 |
| 5822605 | Parallel processor system with a broadcast message serializing circuit provided within a network | Tatsuo Higuchi, Tadaaki Isobe, Junji Nakagoshi, Shigeo Takeuchi, Tatsuru Toba +3 more | 1998-10-13 |
| 5809539 | Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs | Tadayuki Sakakibara, Yoshiko Tamaki | 1998-09-15 |
| 5754876 | Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner | Yoshiko Tamaki, Tadayuki Sakakibaraa | 1998-05-19 |
| 5754792 | Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same | Shinichi Shutoh, Junji Nakagoshi, Naoki Hamanaka, Shigeo Takeuchi | 1998-05-19 |
| 5742766 | Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof | Shigeo Takeuchi, Hideo Wada, Naoki Hamanaka, Junji Nakagoshi, Yasuhiro Ogata +2 more | 1998-04-21 |
| 5710932 | Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism | Naoki Hamanaka | 1998-01-20 |
| 5617575 | Interprocessor priority control system for multivector processor | Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto, Yasuhiro Inagami +1 more | 1997-04-01 |
| 5590353 | Vector processor adopting a memory skewing scheme for preventing degradation of access performance | Tadayuki Sakakibara, Yoshiko Tamaki, Katsuyoshi Kitai, Yasuhiro Inagami | 1996-12-31 |
| 5530881 | Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs | Yasuhiro Inagami, Yoshiko Tamaki, Katsuyoshi Kitai, Tadayuki Sakakibara | 1996-06-25 |
| 5517619 | Interconnection network and crossbar switch for the same | Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Shigeo Nagashima | 1996-05-14 |
| 5506980 | Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory | Yasuhiro Inagami, Yoshiko Tamaki, Katsuyoshi Kitai, Tadayuki Sakakibara | 1996-04-09 |
| 5465380 | Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs | Naoki Hamanaka, Koichiro Omoda, Shigeo Nagashima | 1995-11-07 |
| 5437043 | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers | Hiroaki Fujii, Naoki Hamanaka, Yasuhiro Inagami, Yoshiko Tamaki | 1995-07-25 |
| 5392443 | Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data | Tadayuki Sakakibara, Katsuyoshi Kitai, Yasuhiro Inagami, Yoshiko Tamaki, Tadaaki Isobe +2 more | 1995-02-21 |
| 5339396 | Interconnection network and crossbar switch for the same | Akira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Shigeo Nagashima | 1994-08-16 |
| 5339429 | Parallel processing system and compiling method used therefor | Yasuhiro Inagami, Yoshiko Tamaki, Tadayuki Sakakibara, Katsuyoshi Kitai | 1994-08-16 |
| 5301322 | System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system | Naoki Hamanaka, Koichiro Omoda, Shigeo Nagashima | 1994-04-05 |