Issued Patents All Time
Showing 25 most recent of 445 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12401010 | 3D processor having stacked integrated circuit die | Ilyas Mohammed, Kenneth Duong, Javier A. Delacruz | 2025-08-26 |
| 12387092 | Neural network loss function that incorporates incorrect category probabilities | Philip Sharos | 2025-08-12 |
| 12367661 | Weighted selection of inputs for training machine-trained network | Eric A. Sather, Andrew Siegel, Evgeny Sorkin | 2025-07-22 |
| 12362182 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Shaowu Huang, William C. Plants, David Edward Fisch | 2025-07-15 |
| 12322182 | Visual wake content for image processing | Serdar Kizilgul, Murali Dharan | 2025-06-03 |
| 12299068 | Reduced dot product computation circuit | Kenneth Duong, Jung Ko | 2025-05-13 |
| 12299555 | Training network with discrete weight values | Eric A. Sather | 2025-05-13 |
| 12293993 | 3D chip sharing data bus | Javier A. Delacruz, Ilyas Mohammed | 2025-05-06 |
| 12265905 | Computation of neural network node with large input values | Jung Ko, Kenneth Duong | 2025-04-01 |
| 12260317 | Compiler for implementing gating functions for neural network configuration | Brian Thomas | 2025-03-25 |
| 12248880 | Using batches of training items for training a network | Eric A. Sather, Andrew C. Mihal | 2025-03-11 |
| 12248869 | Three dimensional circuit implementing machine trained network | Kenneth Duong | 2025-03-11 |
| 12218059 | Stacked IC structure with orthogonal interconnect layers | Ilyas Mohammed, Javier A. Delacruz | 2025-02-04 |
| 12217160 | Allocating blocks of unified memory for integrated circuit executing neural network | Jung Ko, Kenneth Duong, Won-woo Rhee | 2025-02-04 |
| 12190230 | Computation of neural network node by neural network inference circuit | Kenneth Duong, Jung Ko | 2025-01-07 |
| 12175368 | Training sparse networks with discrete weight values | Eric A. Sather | 2024-12-24 |
| 12165043 | Data transfer for non-dot product computations on neural network inference circuit | Jung Ko, Kenneth Duong | 2024-12-10 |
| 12165055 | Storing of intermediate computed values for subsequent use in a machine trained network | Ryan James Cassidy | 2024-12-10 |
| 12165066 | Training network to maximize true positive rate at low false positive rate | Eric A. Sather, Andrew C. Mihal | 2024-12-10 |
| 12165069 | Compiler for optimizing number of cores used to implement neural network | Brian Thomas | 2024-12-10 |
| 12159214 | Buffering of neural network inputs and outputs | Jung Ko, Kenneth Duong, Won-woo Rhee | 2024-12-03 |
| 12142528 | 3D chip with shared clock distribution network | Javier A. Delacruz, Ilyas Mohammed, Eric Nequist | 2024-11-12 |
| 12136039 | Optimizing global sparsity for neural network | Eric A. Sather | 2024-11-05 |
| 12124939 | Generation of machine-trained network instructions | Justin Tantiongloc, Brian Thomas | 2024-10-22 |
| 12118463 | Weight value decoder of neural network inference circuit | Kenneth Duong, Jung Ko | 2024-10-15 |