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Methods, systems and apparatus for in-field testing for generic diagnostic components |
Asad Azam, R Selvakumar Raja Gopal, Kaitlyn Chen |
2022-05-17 |
| 11257560 |
Test architecture for die to die interconnect for three dimensional integrated circuits |
Fei Su, Puneet Gupta, Wei Ming Lim, Terrence Huat Hin Tan, Amit Sanghani +4 more |
2022-02-22 |
| 10859627 |
In-field system testing |
Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah +3 more |
2020-12-08 |
| 10491381 |
In-field system test security |
Neel Shah, Kirk S. Yap, Amy L. Santoni, Michael Neve de Mevergnies, Oscar Mendoza +3 more |
2019-11-26 |
| 9256505 |
Data transformations to improve ROM yield and programming time |
— |
2016-02-09 |
| 8793549 |
Low-cost design for register file testability |
— |
2014-07-29 |
| 8711645 |
Victim port-based design for test area overhead reduction in multiport latch-based memories |
— |
2014-04-29 |
| 8656233 |
Scan cell designs with serial and parallel loading of test data |
— |
2014-02-18 |
| 8583973 |
Stored-pattern logic self-testing with serial communication |
— |
2013-11-12 |
| 8499230 |
Critical path monitor for an integrated circuit and method of operation thereof |
— |
2013-07-30 |
| 8473792 |
Logic BIST for system testing using stored patterns |
— |
2013-06-25 |
| 8473890 |
Timing error sampling generator and a method of timing testing |
Alexander Tetelbaum |
2013-06-25 |
| 8464198 |
Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit |
— |
2013-06-11 |
| 8418008 |
Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit |
Narendra B. Devta-Prasa, Arun Gunda, Fan Yang |
2013-04-09 |
| 8228750 |
Low cost comparator design for memory BIST |
— |
2012-07-24 |
| 8191029 |
Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing |
Alexander Tetelbaum |
2012-05-29 |
| 8090965 |
System and method for testing memory power management modes in an integrated circuit |
— |
2012-01-03 |
| 8010935 |
Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit |
Alexander Tetelbaum |
2011-08-30 |
| 7971169 |
System and method for reducing the generation of inconsequential violations resulting from timing analyses |
Alexander Tetelbaum, Nicholas Callegari |
2011-06-28 |
| 7802159 |
Enhanced logic built-in self-test module and method of online system testing employing the same |
Narendra Devta-Prasanna, Fan Yang |
2010-09-21 |
| 6598211 |
Scaleable approach to extracting bridges from a hierarchically described VLSI layout |
Sujit T. Zachariah |
2003-07-22 |
| 6519499 |
Method and apparatus for extracting bridges from an integrated circuit layout |
Sujit T. Zachariah, Carl D. Roth |
2003-02-11 |
| 6502004 |
Method and apparatus for extracting bridges from an integrated circuit layout |
Sujit T. Zachariah, Carl D. Roth |
2002-12-31 |