Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430127 | Vector test decimal instruction for validity testing | Michael Klein, Kerstin Claudia Schelm, Petra Leber, Andreas Wagner, Bruce C. Giamei +3 more | 2025-09-30 |
| 11886848 | Binary translation using raw binary code with compiler produced metadata | Toshihiko Koju, David Kevin Siegwart, Jordan Ryan Zannier, Allan H. Kielstra | 2024-01-30 |
| 11663004 | Vector convert hexadecimal floating point to scaled decimal instruction | Eric M. Schwarz, Kerstin Claudia Schelm, Petra Leber, Silvia M. Mueller, Xin Guo +1 more | 2023-05-30 |
| 11620153 | Instruction interrupt suppression of overflow exception | Cedric Lichtenau, Jonathan D. Bradbury, Petra Leber | 2023-04-04 |
| 11593080 | Eliminating dead stores | Jordan Ryan Zannier | 2023-02-28 |
| 11531546 | Hexadecimal floating point multiply and add instruction | Eric M. Schwarz, Stefan Payer, Petra Leber, Kerstin Claudia Schelm, Michael Klein +2 more | 2022-12-20 |
| 11442726 | Vector pack and unpack instructions | Eric M. Schwarz, Timothy J. Slegel, Jonathan D. Bradbury, Michael Klein, Xin Guo | 2022-09-13 |
| 11360769 | Decimal scale and convert and split to hexadecimal floating point instruction | Eric M. Schwarz, Petra Leber, Kerstin Claudia Schelm, Silvia M. Mueller, Xin Guo +1 more | 2022-06-14 |
| 11099853 | Digit validation check control in instruction execution | Cedric Lichtenau, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo | 2021-08-24 |
| 11068246 | Control flow graph analysis | Toshihiko Koju | 2021-07-20 |
| 11023205 | Negative zero control in instruction execution | Cedric Lichtenau, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo | 2021-06-01 |
| 11003453 | Branch target buffer for emulation environments | Carlos D. Cavanna, Chad McIntyre, Ali I. Sheikh | 2021-05-11 |
| 10990390 | Decimal load immediate instruction | Jonathan D. Bradbury, Silvia M. Mueller | 2021-04-27 |
| 10776255 | Automatic verification of optimization of high level constructs using test vectors | Iain A. Ireland, Allan H. Kielstra, David Kevin Siegwart, Toshihiko Koju | 2020-09-15 |
| 10725780 | Convert to zoned format from decimal floating point format | Steven R. Carlough, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2020-07-28 |
| 10719324 | Convert to zoned format from decimal floating point format | Steven R. Carlough, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2020-07-21 |
| 10664252 | Inserting implicit sequence points into computer program code to support debug operations | Christopher E. Bowler, Chen Chen, Tommy U. Hoffner, Tarique M. Islam, Raul E. Silvera | 2020-05-26 |
| 10534612 | Hybrid polymorphic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments | Carlos D. Cavanna, Chad McIntyre, Ali I. Sheikh | 2020-01-14 |
| 10430185 | Decimal load immediate instruction | Jonathan D. Bradbury, Silvia M. Mueller | 2019-10-01 |
| 10346134 | Perform sign operation decimal instruction | Jonathan D. Bradbury, Silvia M. Mueller, Timothy J. Slegel | 2019-07-09 |
| 10331408 | Decimal multiply and shift instruction | Jonathan D. Bradbury, Steven R. Carlough, Silvia M. Mueller | 2019-06-25 |
| 10303478 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2019-05-28 |
| 10296344 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2019-05-21 |
| 10241757 | Decimal shift and divide instruction | Jonathan D. Bradbury, Steven R. Carlough, Silvia M. Mueller, Eric M. Schwarz | 2019-03-26 |
| 10235170 | Decimal load immediate instruction | Jonathan D. Bradbury, Silvia M. Mueller | 2019-03-19 |