Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9673208 | Method of forming memory array and logic devices | Jinho Kim, Chien-Sheng Su, Feng Zhou, Xian Liu, Nhan Do +1 more | 2017-06-06 |
| 9293359 | Non-volatile memory cells with enhanced channel region effective width, and method of making same | Nhan Do, Hieu Van Tran, Chien-Sheng Su | 2016-03-22 |
| 8461640 | FIN-FET non-volatile memory cell, and an array and method of manufacturing | Yaw Wen Hu | 2013-06-11 |
| 7974136 | Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio | Geeng-Chuan Chern, Ben Sheen, Jonathan Pabustan, Der-Tsyr Fan, Yaw Wen Hu | 2011-07-05 |
| 7800159 | Array of contactless non-volatile memory cells | Yuniarto Widjaja, Henry A. O'M'Mani, Bomy Chen | 2010-09-21 |
| 7718488 | Process of fabricating flash memory with enhanced program and erase coupling | Chiou-Feng Chen, Der-Tsyr Fan | 2010-05-18 |
| 7668013 | Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio | Geeng-Chuan Chern, Ben Sheen, Jonathan Pabustan, Der-Tsyr Fan, Yaw Wen Hu | 2010-02-23 |
| 7646641 | NAND flash memory with nitride charge storage gates and fabrication process | Chiou-Feng Chen, Der-Tsyr Fan | 2010-01-12 |
| 7598561 | NOR flash memory | Bomy Chen, Der-Tsyr Fan | 2009-10-06 |
| 7501321 | NAND flash memory with densely packed memory gates and fabrication process | Der-Tsyr Fan, Chiou-Feng Chen | 2009-03-10 |
| 7217621 | Self-aligned split-gate NAND flash memory and fabrication process | Chiou-Feng Chen, Caleb Yu-Sheng Cho, Ming-Jer Chen, Der-Tsyr Fan | 2007-05-15 |
| 7215573 | Method and apparatus for reducing operation disturbance | Tseng-Yi Liu, Ben Sheen | 2007-05-08 |
| 7046552 | Flash memory with enhanced program and erase coupling and process of fabricating the same | Chiou-Feng Chen, Der-Tsyr Fan | 2006-05-16 |
| 7037787 | Flash memory with trench select gate and fabrication process | Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen | 2006-05-02 |
| 6992929 | Self-aligned split-gate NAND flash memory and fabrication process | Chiou-Feng Chen, Caleb Yu-Sheng Cho, Ming-Jer Chen, Der-Tsyr Fan | 2006-01-31 |
| 6894339 | Flash memory with trench select gate and fabrication process | Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen | 2005-05-17 |
| 6885586 | Self-aligned split-gate NAND flash memory and fabrication process | Chiou-Feng Chen, Der-Tsyr Fan, Jung-Chang Lu | 2005-04-26 |
| 6747310 | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication | Der-Tsyr Fan, Chiou-Feng Chen | 2004-06-08 |
| 6171907 | Method for fabricating tunnel window in EEPROM cell with reduced cell pitch | — | 2001-01-09 |
| 5407840 | Method for simultaneously fabricating bipolar and complementary field effect transistors | Juliana Manoliu | 1995-04-18 |
| 5179031 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany | 1993-01-12 |
| 5124817 | Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany | 1992-06-23 |
| 5023193 | Method for simultaneously fabricating bipolar and complementary field effect transistors using a minimal number of masks | Juliana Manoliu | 1991-06-11 |
| 5001081 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany | 1991-03-19 |
| 4727046 | Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases | Juliana Manoliu | 1988-02-23 |