Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8148799 | Self-aligned bipolar transistor structure | Alexei Sadovnikov, Jamal Ramdani | 2012-04-03 |
| 7687887 | Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter | Alexei Sadovnikov, Jamal Ramdani | 2010-03-30 |
| 6091111 | High voltage mos device having an extended drain region with different dopant species | Esin Kutlu Demirlioglu | 2000-07-18 |
| 5953599 | Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide | — | 1999-09-14 |
| 5893742 | Co-implantation of arsenic and phosphorus in extended drain region for improved performance of high voltage NMOS device | Esin Kutlu Demirlioglu | 1999-04-13 |
| 5846866 | Drain extension regions in low voltage lateral DMOS devices | Robert Huang | 1998-12-08 |
| 5766990 | Method of manufacturing a high speed bipolar transistor in a CMOS process | — | 1998-06-16 |
| 5179031 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Michael P. Brassington, Reda R. Razouk, Prateep Tuntasood | 1993-01-12 |
| 5124817 | Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Michael P. Brassington, Reda R. Razouk, Prateep Tuntasood | 1992-06-23 |
| 5082796 | Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers | Michael P. Brassington, Reda R. Razouk | 1992-01-21 |
| 5081518 | Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers | Michael P. Brassington, Reda R. Razouk | 1992-01-14 |
| 5001081 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Prateep Tuntasood, Michael P. Brassington, Reda R. Razouk | 1991-03-19 |