Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5859448 | Alternative silicon chip geometries for integrated circuits | — | 1999-01-12 |
| 5780912 | Asymmetric low power MOS devices | James B. Burr | 1998-07-14 |
| 5773863 | Low power, high performance junction transistor | James B. Burr | 1998-06-30 |
| 5719422 | Low threshold voltage, high performance junction transistor | James B. Burr | 1998-02-17 |
| 5650340 | Method of making asymmetric low power MOS devices | James B. Burr | 1997-07-22 |
| 5622880 | Method of making a low power, high performance junction transistor | James B. Burr | 1997-04-22 |
| 5350705 | Ferroelectric memory cell arrangement having a split capacitor plate structure | Andreas Papaliolios | 1994-09-27 |
| 5337279 | Screening processes for ferroelectric memory devices | Anne Gregory, Shi-Qing Wang, Norman E. Abt | 1994-08-09 |
| 5262982 | Nondestructive reading of a ferroelectric capacitor | Reza Moazzami | 1993-11-16 |
| 5179031 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Reda R. Razouk, Monir H. El-Diwany, Prateep Tuntasood | 1993-01-12 |
| 5124817 | Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Reda R. Razouk, Monir H. El-Diwany, Prateep Tuntasood | 1992-06-23 |
| 5082796 | Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers | Monir H. El-Diwany, Reda R. Razouk | 1992-01-21 |
| 5081518 | Use of a polysilicon layer for local interconnect in a CMOS or BICMOS technology incorporating sidewall spacers | Monir H. El-Diwany, Reda R. Razouk | 1992-01-14 |
| 5001081 | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide | Prateep Tuntasood, Reda R. Razouk, Monir H. El-Diwany | 1991-03-19 |