Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11914521 | Cache quota control | Wolfgang H. Klingauf, Muhammad Umer Amjad, Connie W. Cheung, Yueh-Ta Wu, John H. Kelm | 2024-02-27 |
| 11232033 | Application aware SoC memory cache partitioning | Wolfgang H. Klingauf, Connie W. Cheung, Rohit Gupta, Rohit Natarajan, Vanessa Cristina Heppolette +1 more | 2022-01-25 |
| 11138111 | Parallel coherence and memory cache processing pipelines | Srinivasa Rangan Sridharan, Harshavardhan Kaushikkar, Sridhar Kotha, Brian P. Lilly | 2021-10-05 |
| 10970223 | Cache drop feature to increase memory bandwidth and save power | Wolfgang H. Klingauf, Kenneth C. Dyke, Karthik Ramani, Winnie W. Yeung, Anthony P. DeLaurier +3 more | 2021-04-06 |
| 10289565 | Cache drop feature to increase memory bandwidth and save power | Wolfgang H. Klingauf, Kenneth C. Dyke, Karthik Ramani, Winnie W. Yeung, Anthony P. DeLaurier +3 more | 2019-05-14 |
| 9823730 | Power management of cache duplicate tags | Erik P. Machnicki | 2017-11-21 |
| 9454482 | Duplicate tag structure employing single-port tag RAM and dual-port state RAM | Harshavardhan Kaushikkar, Odutola Oluseye Ewedemi | 2016-09-27 |
| 9317102 | Power control for cache structures | Gurjeet S. Saund, Harshavardhan Kaushikkar, Erik P. Machnicki, Seye Ewedemi | 2016-04-19 |
| 9176913 | Coherence switch for I/O traffic | Timothy J. Millet, Shailendra Desai | 2015-11-03 |
| 9021306 | Debug access mechanism for duplicate tag storage | Harshavardhan Kaushikkar, Gurjeet S. Saund, Odutola Oluseye Ewedemi | 2015-04-28 |