Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8954915 | Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit | Yiu-Hing Chan, Shyam Ramji, Paul G. Villarrubia | 2015-02-10 |
| 7908308 | Carry-select adder structure and method to generate orthogonal signal levels | Wilhelm Haller, Ricardo H. Nigaglioni, Hartmut Sturm | 2011-03-15 |
| 7676779 | Logic block timing estimation using conesize | Reinaldo A. Bergamaschi, Sean Michael Carey, Brian W. Curran, Prabhakar Kudva, Matthew E. Mariani +1 more | 2010-03-09 |
| 4967151 | Method and apparatus for detecting faults in differential current switching logic circuits | Arnold E. Barish, David Kiesling, Walter A. Svarczkopf | 1990-10-30 |