Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7751251 | Current sensing scheme for non-volatile memory | — | 2010-07-06 |
| 7583559 | Two transistor wordline decoder output driver | Hari Giduturi, Hernan A. Castro | 2009-09-01 |
| 6772273 | Block-level read while write method and apparatus | Kerry D. Tedrow | 2004-08-03 |
| 6744671 | Kicker for non-volatile memory drain bias | Ritesh B. Trivedi, Robert Baltar, Sandeep Guliani, Balajl Srinivasan | 2004-06-01 |
| 6570789 | Load for non-volatile memory drain bias | Ritesh B. Trivedi, Robert Baltar, Sandeep Guliani, Balaji Srinivasan | 2003-05-27 |
| 6535423 | Drain bias for non-volatile memory | Ritesh B. Trivedi, Robert Baltar, Sandeep Guliani, Balaji Srinivasan | 2003-03-18 |
| 6483742 | Bit map addressing schemes for flash memory | Sherif Sweha | 2002-11-19 |
| 6477086 | Local sensing of non-volatile memory | Ritesh B. Trivedi, Sandeep Guliani, Balaji Srinivasan, Kerry D. Tedrow | 2002-11-05 |
| 6434049 | Sample and hold voltage reference source | Ritesh B. Trivedi, Robert Baltar, Sandeep Guliani, Balaji Srinivasan | 2002-08-13 |
| 6097637 | Dynamic single bit per cell to multiple bit per cell memory | Sanjay S. Talreja, Phillip M. L. Kwong, Duane R. Mills, Rodney R. Rozman | 2000-08-01 |
| 5828616 | Sensing scheme for flash memory with multilevel cells | Sanjay S. Talreja, Albert Fazio, Gregory E. Atwood, Johnny Javanifard, Kevin W. Frary | 1998-10-27 |
| 5822256 | Method and circuitry for usage of partially functional nonvolatile memory | Steven Wells, David M. Brown, Johnny Javanifard, Sherif Sweha, Robert Nasry Hasbun +7 more | 1998-10-13 |
| 5815443 | Bit map addressing schemes for flash memory | Sherif Sweha | 1998-09-29 |
| 5801991 | Deselected word line that floats during MLC programming of a flash memory | Stephen N. Keeney, Albert Fazio, Ken Wojciechowski | 1998-09-01 |
| 5796667 | Bit map addressing schemes for flash memory | Sherif Sweha | 1998-08-18 |
| 5781472 | Bit map addressing schemes for flash/memory | Sherif Sweha | 1998-07-14 |
| 5754566 | Method and apparatus for correcting a multilevel cell memory by using interleaving | Mark Christopherson | 1998-05-19 |
| 5748546 | Sensing scheme for flash memory with multilevel cells | Sanjay S. Talreja, Kevin W. Frary, Gregory E. Atwood, Albert Fazio, Johnny Javanifard | 1998-05-05 |
| 5663923 | Nonvolatile memory blocking architecture | Robert Baltar, Kevin W. Frary, Steven D. Pudar, Sherif Sweha | 1997-09-02 |
| 5539690 | Write verify schemes for flash memory with multilevel cells | Sanjay S. Talreja, Kevin W. Frary, Phillip M. L. Kwong | 1996-07-23 |
| 5523972 | Method and apparatus for verifying the programming of multi-level flash EEPROM memory | Mamun Ur Rashid, Chakravarthy Yarlagadda, Phillip M. L. Kwong, Albert Fazio | 1996-06-04 |
| 5517138 | Dual row selection using multiplexed tri-level decoder | Robert Baltar | 1996-05-14 |
| 5508958 | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage | Albert Fazio, Gregory E. Atwood | 1996-04-16 |
| 5497354 | Bit map addressing schemes for flash memory | Sherif Sweha | 1996-03-05 |
| 5485422 | Drain bias multiplexing for multiple bit flash cell | Kevin W. Frary, Sanjay S. Talreja | 1996-01-16 |