Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12219750 | Memory device having 2-transistor vertical memory cell and separate read and write gates | Eric Carman, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Kamal M. Karda, Karthik Sarpatwari +2 more | 2025-02-04 |
| 12080331 | Memory device having 2-transistor vertical memory cell and shield structures | Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni +1 more | 2024-09-03 |
| 11868220 | Efficient power scheme for redundancy | Richard E. Fackenthal | 2024-01-09 |
| 11778806 | Memory device having 2-transistor vertical memory cell and separate read and write gates | Eric Carman, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Kamal M. Karda, Karthik Sarpatwari +2 more | 2023-10-03 |
| 11747982 | On-demand memory page size | Richard E. Fackenthal | 2023-09-05 |
| 11688450 | Memory device having 2-transistor vertical memory cell and shield structures | Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni +1 more | 2023-06-27 |
| 11605412 | Wear leveling for random access and ferroelectric memory | Richard E. Fackenthal, Daniele Vimercati | 2023-03-14 |
| 11562805 | Speculative section selection within a memory device | Richard E. Fackenthal, Jahanshir J. Javanifard | 2023-01-24 |
| 11222668 | Memory cell sensing stress mitigation | Daniele Vimercati, Richard E. Fackenthal, Yasuko Hattori | 2022-01-11 |
| 11157176 | On demand memory page size | Richard E. Fackenthal | 2021-10-26 |
| 11003361 | Wear leveling | Richard E. Fackenthal | 2021-05-11 |
| 10971203 | Wear leveling for random access and ferroelectric memory | Richard E. Fackenthal, Daniele Vimercati | 2021-04-06 |
| 10872678 | Speculative section selection within a memory device | Richard E. Fackenthal, Jahanshir J. Javanifard | 2020-12-22 |
| 10585597 | Wear leveling | Richard E. Fackenthal | 2020-03-10 |
| 10416903 | Wear leveling | Richard E. Fackenthal | 2019-09-17 |
| 10410709 | Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines | Daniele Vimercati | 2019-09-10 |
| 10394456 | On demand memory page size | Richard E. Fackenthal | 2019-08-27 |
| 10388351 | Wear leveling for random access and ferroelectric memory | Richard E. Fackenthal, Daniele Vimercati | 2019-08-20 |
| 10198195 | Wear leveling | Richard E. Fackenthal | 2019-02-05 |
| 9886991 | Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines | Daniele Vimercati | 2018-02-06 |
| 8331857 | Wireless interface to program phase-change memories | Mostafa Naguib Abdulla, Hari Giduturi | 2012-12-11 |
| 8064278 | Protection register for a non-volatile memory | Chin-Tin Tina Yu, Rich Fackenthal | 2011-11-22 |
| 7823279 | Method for using an in package power supply to supply power to an integrated circuit and to a component | Steven Eskildsen | 2010-11-02 |
| 6564285 | Synchronous interface for a nonvolatile memory | Brian Dipert, Sachidanandan Sambandan, Bruce McCormick, Richard D. Pashley | 2003-05-13 |
| 6385688 | Asynchronous interface for a nonvolatile memory | Brian Dipert, Sachidanandan Sambandan, Bruce McCormick, Richard D. Pashley | 2002-05-07 |