ST

Sanjay S. Talreja

IN Intel: 25 patents #1,576 of 30,777Top 6%
Overall (All Time): #165,007 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8489780 Power saving in NAND flash memory Rajesh Sundaram, Rodney R. Rozman 2013-07-16
6931498 Status register architecture for flexible read-while-write device Jason Panavich, Ramkarthik Ganesan, Terry L. Kendall 2005-08-16
6920539 Method and system to retrieve information Shekoufeh Qawami, Chaitanya Rajguru 2005-07-19
6618790 Burst suspend and resume with computer memory Lance W. Dover, Ramkarthik Ganesan, Ramadurai Rajagopal 2003-09-09
6587373 Multilevel cell memory architecture 2003-07-01
6483743 Multilevel cell memory architecture 2002-11-19
6223290 Method and apparatus for preventing the fraudulent use of a cellular telephone Robert E. Larsen, Peter K. Hazen, Sandeep Guliani, Robert Nasry Hasbun, Collin Ong +2 more 2001-04-24
6154819 Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks Robert E. Larsen, Peter K. Hazen, Sandeep Guliani, Robert Nasry Hasbun, Collin Ong +3 more 2000-11-28
6097637 Dynamic single bit per cell to multiple bit per cell memory Mark E. Bauer, Phillip M. L. Kwong, Duane R. Mills, Rodney R. Rozman 2000-08-01
6088264 Flash memory partitioning for read-while-write operation Peter K. Hazen, Ranjeet Alexis, Robert E. Larsen, Charles W. Brown 2000-07-11
5944837 Controlling flash memory program and erase pulses Rodney R. Rozman, Mickey L. Fandrich, Bharat Pathak 1999-08-31
5933026 Self-configuring interface architecture on flash memories Robert E. Larsen, Harry Q. Pon, Marcus E. Landgraf, Ranjeet Alexis 1999-08-03
5907700 Controlling flash memory program and erase pulses Rodney R. Rozman, Mickey L. Fandrich, Bharat Pathak 1999-05-25
5896338 Input/output power supply detection scheme for flash memory Marcus E. Landgraf, Robert E. Larsen, Mase J. Taub, Vishram Prakash Dalvi, Edward Babb +2 more 1999-04-20
5828616 Sensing scheme for flash memory with multilevel cells Mark E. Bauer, Albert Fazio, Gregory E. Atwood, Johnny Javanifard, Kevin W. Frary 1998-10-27
5748546 Sensing scheme for flash memory with multilevel cells Mark E. Bauer, Kevin W. Frary, Gregory E. Atwood, Albert Fazio, Johnny Javanifard 1998-05-05
5742787 Hardware reset of a write state machine for flash memory 1998-04-21
5684741 Auto-verification of programming flash memory cells 1997-11-04
5539690 Write verify schemes for flash memory with multilevel cells Mark E. Bauer, Kevin W. Frary, Phillip M. L. Kwong 1996-07-23
5485422 Drain bias multiplexing for multiple bit flash cell Mark E. Bauer, Kevin W. Frary 1996-01-16
5438546 Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories Michel Ibrahim Ishac, Mark E. Bauer 1995-08-01
5379413 User selectable word/byte input architecture for flash EEPROM memory write and erase operations Peter K. Hazen, Rodney R. Rozman 1995-01-03
5317535 Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays Duane R. Mills, Jahanshir J. Javanifard, Sachidanandan Sambandan 1994-05-31
5280447 Floating gate nonvolatile memory with configurable erasure blocks Peter K. Hazen, Sherif Sweha 1994-01-18
5267196 Floating gate nonvolatile memory with distributed blocking feature Peter K. Hazen, Sherif Sweha 1993-11-30