| 5828616 |
Sensing scheme for flash memory with multilevel cells |
Mark E. Bauer, Sanjay S. Talreja, Albert Fazio, Gregory E. Atwood, Johnny Javanifard |
1998-10-27 |
| 5748546 |
Sensing scheme for flash memory with multilevel cells |
Mark E. Bauer, Sanjay S. Talreja, Gregory E. Atwood, Albert Fazio, Johnny Javanifard |
1998-05-05 |
| 5663923 |
Nonvolatile memory blocking architecture |
Robert Baltar, Mark E. Bauer, Steven D. Pudar, Sherif Sweha |
1997-09-02 |
| 5539690 |
Write verify schemes for flash memory with multilevel cells |
Sanjay S. Talreja, Mark E. Bauer, Phillip M. L. Kwong |
1996-07-23 |
| 5485422 |
Drain bias multiplexing for multiple bit flash cell |
Mark E. Bauer, Sanjay S. Talreja |
1996-01-16 |
| 5289412 |
High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories |
Sachidanandan Sambandan |
1994-02-22 |
| 5262990 |
Memory device having selectable number of output pins |
Duane F. Mills, Jahanshir J. Javanifard, Rodney R. Rozman, Sherif Sweha |
1993-11-16 |
| 5245574 |
Apparatus for increasing the speed of operation of non-volatile memory arrays |
George R. Canepa, Sherif Sweha |
1993-09-14 |
| 5243575 |
Address transition detection to write state machine interface circuit for flash memory |
Sachidanandan Sambandan, Peter K. Hazen |
1993-09-07 |