Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710376 | Wear leveling for a memory device | — | 2017-07-18 |
| 9104547 | Wear leveling for a memory device | — | 2015-08-11 |
| 6744671 | Kicker for non-volatile memory drain bias | Ritesh B. Trivedi, Mark E. Bauer, Sandeep Guliani, Balajl Srinivasan | 2004-06-01 |
| 6574141 | Differential redundancy multiplexor for flash memory devices | — | 2003-06-03 |
| 6570789 | Load for non-volatile memory drain bias | Ritesh B. Trivedi, Mark E. Bauer, Sandeep Guliani, Balaji Srinivasan | 2003-05-27 |
| 6535423 | Drain bias for non-volatile memory | Ritesh B. Trivedi, Mark E. Bauer, Sandeep Guliani, Balaji Srinivasan | 2003-03-18 |
| 6456540 | Method and apparatus for gating a global column select line with address transition detection | Ritesh B. Trivedi | 2002-09-24 |
| 6446179 | Computing system with volatile lock architecture for individual block locking on flash memory | — | 2002-09-03 |
| 6442069 | Differential signal path for high speed data transmission in flash memory | Balaji Srinivasan, Ritesh B. Trivedi | 2002-08-27 |
| 6434049 | Sample and hold voltage reference source | Ritesh B. Trivedi, Mark E. Bauer, Sandeep Guliani, Balaji Srinivasan | 2002-08-13 |
| 6212099 | Preventing data corruption in a memory device using a modified memory cell conditioning methodology | Suibin Zhang, Ravi Annavajjhala, Dow Ping D. Wong, Marc E. Landgraf | 2001-04-03 |
| 6209069 | Method and apparatus using volatile lock architecture for individual block locking on flash memory | — | 2001-03-27 |
| 5663923 | Nonvolatile memory blocking architecture | Mark E. Bauer, Kevin W. Frary, Steven D. Pudar, Sherif Sweha | 1997-09-02 |
| 5517138 | Dual row selection using multiplexed tri-level decoder | Mark E. Bauer | 1996-05-14 |