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Process for manufacturing an array of cells including selection bipolar junction transistors |
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Method and relative test structure for measuring the coupling capacitance between two interconnect lines |
Luca Bortesi, Alessandro Bogliolo |
2008-04-01 |
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Process for manufacturing an array of cells including selection bipolar junction transistors |
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Electrically erasable and programmable non-volatile memory cell |
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Multi-emitter bipolar transistor for bandgap reference circuits |
Paolo Caprara, Giorgio Oddone, Antonio Barcella |
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Bipolar transistor produced using processes compatible with those employed in the manufacture of MOS device |
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