KW

Kenneth D. Wagner

SG S3 Group: 3 patents #10 of 130Top 8%
IBM: 3 patents #26,272 of 70,183Top 40%
PM Pmc-Sierra: 3 patents #23 of 145Top 20%
PA Philips North America: 2 patents #5 of 28Top 20%
SY Synopsys: 2 patents #669 of 2,302Top 30%
M( Microsemi Solutions (Us): 1 patents #19 of 63Top 35%
Overall (All Time): #319,216 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10607469 Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facility Vikram Devdas, Dan Erichsen, Richard John Heaton 2020-03-31
10198927 Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facility Vikram Devdas, Dan Erichsen, Richard John Heaton 2019-02-05
9922524 Methods for detecting and handling fall and perimeter breach events for residents of an assisted living facility Vikram Devdas, Dan Erichsen, Richard John Heaton 2018-03-20
9779197 Method and system of merging memory cells into multi-bit registers in an integrated circuit layout Howard Chang, Kanwaldeep Singh Chhokar, Redentor De La Merced, Yoo Ho Cho 2017-10-03
9104825 Method of reducing current leakage in a product variant of a semiconductor device Bruce Scatchard, Chunfang Xie, Scott Barrick 2015-08-11
8843870 Method of reducing current leakage in a device and a device thereby formed Bruce Scatchard, Chunfang Xie, Scott Barrick 2014-09-23
8533546 Reconfigurable scan chain connectivity to enable flexible device I/O utilization Kenneth William Ferguson, Steven Yu Peng Ng, Bradley J. Burke, Michel Duchesneau, Aaron John Dennis +1 more 2013-09-10
6389566 Edge-triggered scan flip-flop and one-pass scan synthesis methodology Srinivasan Iyengar, Mehran Amerian 2002-05-14
6169418 Efficient routing from multiple sources to embedded DRAM and other large circuit blocks 2001-01-02
6158033 Multiple input signature testing & diagnosis for embedded blocks in integrated circuits Mehran Amerian 2000-12-05
6067650 Method and apparatus for performing partial unscan and near full scan within design for test applications James Beausang, Robert Walker 2000-05-23
5696771 Method and apparatus for performing partial unscan and near full scan within design for test applications James Beausang, Robert Walker 1997-12-09
5633812 Fault simulation of testing for board circuit failures James Allen, Theresa L. Meyer 1997-05-27
5612963 Hybrid pattern self-testing of integrated circuits Bernd Koenemann, John A. Waicukauski 1997-03-18
5375091 Method and apparatus for memory dynamic burn-in and test Robert W. Berry, Jr., Bernd Koenemann, William J. Scarpero, Jr., Philip G. Shephard, III, Gulsun Yasar 1994-12-20